Using genvar to build delay block(Verilog genvar的使用)

Genvar is widly use when we want to instantiate lots of gates/modules. In this case, we use “genvar” to generate a delay block that uses registers in serial.

Genvar可以独立于always使用，常用来初始化或调用大量重复的模块。本篇将用genvar来设计一个可以自定义的延迟寄存器链：

module delay(q,d,clock);
output [WIDTH-1:0] q;
input [WIDTH -1:0] d;
input clock;

parameter DEPTH = 5; //(how many clocks you want to delay)
parameter WIDTH = 2; //(width of input & output sig)
wire [WIDTH-1:0] a [0:DEPTH];

//-------------code------------//
//ASSIGNMNET
assign a[0] = d;
assign q = a[DEPTH];
// genvar do not need "always" procedure
generate
genvar k;  
for (k = 0; k < DEPTH; k = k + 1) // generate DEPTH regs
begin: delay
register #(WIDTH) reg_delay(a[k+1], a[k], clock); 

end
endgenerate

endmodule 


module register(q, d, clock);
input [WIDTH-1:0] d;
input clock;
output reg [WIDTH-1:0] q = 0;
parameter WIDTH = 16;

always @ (posedge clock)
begin
    q <= d;
end

endmodule