Verilog学习笔记——07——相邻16个数相加

相邻16个数相加

 

代码

//2023-5-17
//相邻16点相加
`timescale 1ns/10ps
module sigma_16p(
datain,
synin,
clk,
res,
dataout,
synout
);

input[7:0] datain;
input synin;
input clk;
input res;
output[11:0] dataout;
output synout;

reg synin1;
wire synpulse;

reg[3:0] cont;
wire[7:0] comp8;
wire[11:0] d12;

reg[11:0] sigma;
reg[11:0] dataout;
reg synout;
assign synpulse = synin & synin1 ;
assign comp8 = datain[7]?{datain[7],~datain[6:0]+1}:datain;
assign d12={comp8[7],comp8[7],comp8[7],comp8[7],comp8};


always@(posedge clk or negedge res)begin
	if(~res)begin
    synin1 <=0;
    cont <=4'b0000;
		sigma <=0;
		dataout <= 0;
		synout <= 0;
	end
	else begin
		synin1 <= ~synin ;
		if(synpulse)begin
			cont <= cont + 1;
		end
		if(synpulse)begin
			if(cont==15)begin
				dataout <= sigma;
				sigma <= d12;
				synout <= 1;
			end
			else begin
			 sigma <= sigma + d12;
			end
		end
		else begin
			synout <= 0;
		end
	end
end
endmodule
//testbench of sigma_16p
module sigma_16p_tb ;
reg clk;
reg res;
reg synin;
reg[7:0] datain;
wire synout;
wire[11:0] dataout;
sigma_16p sigma_16p(
.datain(datain),
.synin(synin),
.clk(clk),
.res(res),
.dataout(dataout),
.synout(synout)
);

initial begin
	clk <= 0;
	res <= 0;
	synin <= 0;
	datain <= 1;
	#16 res = 1;
	#5000 datain = 8'b0000_0010;
	#25000 $stop;
end
always #5 clk = ~clk;
always #100 synin <= ~synin;
 
endmodule
		
		

仿真波形

 

开始时，输入值为00000001    过5000个时钟单位变为00000010