Verilog学习笔记——07——相邻16个数相加

相邻16个数相加

 

代码

//2023-5-17
//相邻16点相加
`timescale 1ns/10ps
module sigma_16p(
datain,
synin,
clk,
res,
dataout,
synout
);

input[7:0] datain;
input synin;
input clk;
input res;
output[11:0] dataout;
output synout;

reg synin1;
wire synpulse;

reg[3:0] cont;
wire[7:0] comp8;
wire[11:0] d12;

reg[11:0] sigma;
reg[11:0] dataout;
reg synout;
assign synpulse = synin & synin1 ;
assign comp8 = datain[7]?{datain[7],~datain[6:0]+1}:datain;
assign d12={comp8[7],comp8[7],comp8[7],comp8[7],comp8};


always@(posedge clk or negedge res)begin
	if(~res)begin
    synin1 <=0;
    cont <=4'b0000;
		sigma <=0;
		dataout <= 0;
		synout <= 0;
	end
	else be