分频之前仿真成功,分频后代码:
`timescale 1s / 1ms
module Mealy_sequence_detector(A,CP,CR,current_state,next_state);
input A,CR,CP;
output reg [2:0] current_state;
output reg [2:0] next_state;
parameter S0=3'b000,S1=3'b110,S2=3'b010,S3=3'b011,S4=3'b001,S5=3'b101;
parameter S6=3'b100,S7=3'b111;
parameter WIDTH = 27;
reg [WIDTH-1:0]count;
reg CP0;
always@(negedge CP)
begin
//if(CR==0) begin count<=0;CP0<=0;end //if cannot operate the same parameter in parallel
//134217726
if(count<27'd134217726) begin count<=count+1 ;end
else if(count==27'd134217726)begin count<=27'd0;CP0<=~CP0; end
end
always @(negedge CP0 or negedge CR)
begin
if(~CR) current_state<=S0;
else current_state=next_state;
end
always @(current_state or A)
begin
case(current_state)
S7:next_state=S0;
S0:next_state=S1;
S1:next_state=(A==1)?S6:S2;
S2:next_state=(A==1)?S1:S3;
S3:next_state=(A==1)?S2:S4;
S4:next_state=(A==1)?S3:S5;
S5:next_state=(A==1)?S4:S6;
S6:if(A==1)
next_state=S5;
else
next_state=S1;
default:next_state=S0;
endcase
end
endmodule
测试代码:
`timescale 1ns / 1ps
module tb_conditionmachineTest;
reg A,CP,CR;
wire [2:0]current_state;
wire [2:0]next_state;
parameter clk_period = 2;
initial begin
CP=0;
A=0;
CR=1;
forever
#(clk_period/2) CP = ~CP;
end
Mealy_sequence_detector what(
.A(A),
.CP(CP),
.CR(CR),
.current_state(current_state),
.next_state(next_state) //do not add douhao at the last
);
endmodule
结果:
原因暂未查明。