Verilog 7分频，用状态机写的，编译仿真100%通过。

/* 7分频*/
module div7_f (
  input d_clk ,
  input d_rst ,
  output reg clk_div_7
) ;

parameter s0=7'b0000001;
parameter s1=7'b0000010;
parameter s2=7'b0000100;
parameter s3=7'b0001000;
parameter s4=7'b0010000;
parameter s5=7'b0100000;
parameter s6=7'b1000000;

reg [6:0] curr_st;
reg [6:0] next_st;

always @(posedge d_clk or   negedge d_rst )
  begin 
  if (~d_rst)
  curr_st <= s0;
  else
  curr_st <=next_st;
  end 
  

 always @(* )
  begin 
  case (curr_st)
  s0: next_st = s1;
  s1: next_st = s2;
  s2: next_st = s3;
  s3: next_st = s4;
  s4: next_st = s5;
  s5: next_st = s6;
  s6: next_st = s0;
  default : next_st= s0 ;
  endcase 
  end
  
always @(posedge d_clk or  negedge d_rst )
  begin 
  if (~d_rst)
  clk_div_7 <= 1'b0;
  else if ((curr_st == s0) | (curr_st == s1) | (curr_st == s2) | (curr_st == s3))
  clk_div_7 <= 1'b0;
  else if ((curr_st == s4) | (curr_st == s5) | (curr_st == s6))
  clk_div_7 <= 1'b1;
  else 
  clk_div_7 <= 1'b0;
  end  
  
  endmodule