基于CORDIC的正余弦波形生成

//============================================================
//  文件名：    CordicRotator.v
//  功能描述：    Cordic旋转，旋转模式
//  创建日期：    2017-3-6
//============================================================
module CordicRotator #(
       parameter accuracy_bits=16,
          protect_bits=4  //保护位宽度为以2为底的accuracy_bits的对数
       )
      (
      clk,rst,en,
      xi,yi,zi,
      shift_bits,
      phase_quadrant_in,
      phase_rotate,
      xo,yo,zo,
      phase_quadrant_out
      );
//============================================================
//输入输出端口
//============================================================
input              clk;    //输入时钟
input              rst;    //复位信号，低电平有效
input              en;    //使能信号
input  signed [accuracy_bits+protect_bits-1'b1:0] xi;     //输入xi
input  signed  [accuracy_bits+protect_bits-1'b1:0] yi;     //输入yi
input  signed [accuracy_bits+protect_bits-1'b1:0] zi;     //输入相位角
input    [3:0]         shift_bits;   //移位位数
input    [1:0]         phase_quadrant_in;//相位象限位置
input  signed  [accuracy_bits-1'b1:0]    phase_rotate;  //旋转角度
output reg signed [accuracy_bits+protect_bits-1'b1:0] xo;     //输出xo
output reg signed [accuracy_bits+protect_bits-1'b1:0] yo;     //输出yo
output reg signed [accuracy_bits+protect_bits-1'b1:0] zo;     //相位输出
output reg   [1:0]         phase_quadrant_out;//相位象限位置输出

//============================================================
//逻辑功能实现
//============================================================
//---------------------------------------------------------------------------------------------
//相位象限寄存
//---------------------------------------------------------------------------------------------
always@(posedge clk or negedge rst)
begin
 if(!rst)
  phase_quadrant_out<=2'd0;
 else if(!en)
  phase_quadrant_out<=2'd0;
 else
  phase_quadrant_out<=phase_quadrant_in;
end
//---------------------------------------------------------------------------------------------
//输出xo计算
//---------------------------------------------------------------------------------------------
always@(posedge clk or negedge rst)
begin
 if(!rst)
  xo<={(accuracy_bits+protect_bits){1'b0}};
 else if(!en)
  xo<={(accuracy_bits+protect_bits){1'b0}};
 else if(zi[accuracy_bits+protect_bits-1'b1])
  xo<=xi+(yi>>>shift_bits);
 else
  xo<=xi-(yi>>>shift_bits);
end