异步FIFO代码

最新推荐文章于 2023-05-06 15:52:27 发布

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最新推荐文章于 2023-05-06 15:52:27 发布

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分类专栏： LWLA系列逻辑分析仪 VERILOG ZYNQ7

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/*
  dc_fifo_gray #( parameter dw = 64,aw=7) (
	  .rd_clk( ), 
	  .wr_clk( ), 
	  .rd_rst_n( ),
	  .wr_rst_n( ),
	  .we( ),
	  .re( ),      
	  .din( )  ,      
	  .dout ( ) ,
      .full( ) , 	
	  .empty( ) 	  
    );


*/

module dc_fifo_gray #( parameter dw = 64,aw=7) (
        input	rd_clk, wr_clk, rd_rst_n,wr_rst_n,we,re,
        input	[dw-1:0]	din ,
        output	[dw-1:0]	dout ,
        output		reg 	full , 	empty
    );
    //synopsys sync_set_reset "rd_rst_n","wr_rst_n"
 

    wire legal_we = we & (~full) ;
    wire legal_re = re & (~empty) ;

    reg	[aw:0]		wp_bin, wp_gray;
    reg	[aw:0]		rp_bin, rp_gray;
    reg	[aw:0]		wp_s, rp_s;
    reg	[aw:0]		wp_r, rp_r;// add by liwei

    wire	[aw:0]		wp_bin_next, wp_gray_next;
    wire	[aw:0]		rp_bin_next, rp_gray_next;
    wire	[aw:0]		wp_bin_x, rp_bin_x;

    simple_dc_ram  simple_dc_ram ( 
                            .rd_clk(rd_clk),
                            .wr_clk(wr_clk	),
                            .wr(legal_we),
                            .wr_addr(wp_bin[aw-1:0]),
                            .rd_addr(rp_bin[aw-1:0]	),
                            .q(dout ) ,
                            .d(din)
                        );

    always @(posedge wr_clk)
        if(!wr_rst_n)	wp_bin <= {aw+1{1'b0}};
        else
            if(legal_we)		wp_bin <= wp_bin_next;

    always @(posedge wr_clk)
        if(!wr_rst_n)	wp_gray <= {aw+1{1'b0}};
        else
            if(legal_we)		wp_gray <= wp_gray_next;

    assign wp_bin_next  = wp_bin + {{aw{1'b0}},1'b1};
    assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[aw:1]};

    always @(posedge rd_clk)
        if(!rd_rst_n)	rp_bin <= {aw+1{1'b0}};
        else
            if(legal_re)		rp_bin <= rp_bin_next;

    always @(posedge rd_clk)
        if(!rd_rst_n)	rp_gray <= {aw+1{1'b0}};
        else
            if(legal_re)		rp_gray <= rp_gray_next;

    assign rp_bin_next  = rp_bin + {{aw{1'b0}},1'b1};
    assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[aw:1]};

    always @(posedge rd_clk)	wp_r <= wp_gray;
    always @(posedge rd_clk)	wp_s <= wp_r;

    // read pointer
    always @(posedge wr_clk)	rp_r <= rp_gray;
    always @(posedge wr_clk)	rp_s <= rp_r;

    genvar i;

    assign wp_bin_x[aw] = wp_s[aw];
    generate
        //  assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[aw:1]};	// convert gray to binary
        for (i = (aw-1) ; i >= 0; i = i - 1) begin : WP_G2B
            assign wp_bin_x[i] = wp_s[i] ^  wp_bin_x[i+1] ;
        end

        endgenerate


    assign  rp_bin_x[aw] = rp_s[aw];
    generate
        //  assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[aw:1]};	// convert gray to binary
        for (i = (aw-1) ; i >= 0; i = i - 1) begin : RP_G2B
            assign rp_bin_x[i] = rp_s[i] ^  rp_bin_x[i+1] ;
        end

        endgenerate


            always @(posedge rd_clk)
                empty <= (wp_s == rp_gray) | (legal_re & (wp_s == rp_gray_next));

    always @(posedge wr_clk)
        full <= ((wp_bin[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin[aw] != rp_bin_x[aw])) |
             (legal_we & (wp_bin_next[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin_next[aw] != rp_bin_x[aw]));


endmodule





module simple_dc_ram#( parameter dw = 64,aw=7) ( //    48BIT X 8 (8 places ) if replacement nessary ?
        input rd_clk,wr_clk,wr,///wr_clk ~300Mhz   rd_clk~32Mhz
        input [aw-1:0]wr_addr,rd_addr,
        output reg [dw-1:0]q ,
        input [dw-1:0]d
    );
    //instanced (3 + 5 = 8 ) places ,
    reg	[dw-1:0]	mem [(1<<aw)-1:0];
    always @(posedge rd_clk)	q <=  mem[rd_addr];
    always @(posedge wr_clk) if (wr) mem[wr_addr] <=  d;
endmodule