同步fifo及异步fifo的代码示例

同步fifo

module fifo_sync(
					clk,
					rst,
					w_en,
					r_en,
					data_in,
					data_out,
					count,
					full,
					empty
					);
	parameter fifo_data_size = 3;
	parameter fifo_addr_size = 2;
						
	input clk;
	input rst;
	input w_en;
	input r_en;
	input  [fifo_data_size-1:0] data_in;
	output [fifo_data_size-1:0] data_out;
	output full;
	output empty;
	output [fifo_addr_size-1:0] count;
	
	reg [fifo_data_size-1:0] data_out;
	reg [fifo_addr_size:0]	 count;
	reg [fifo_addr_size-1:0] w_addr;
	reg [fifo_addr_size-1:0] r_addr;
	reg [fifo_data_size-1:0] mem[{
   fifo_addr_size{
   1'b1}}:0];
	integer i;
	
	//写操作
	always@(posedge clk or negedge rst)
		begin
			if(!rst)
				begin
					w_addr <= 0;
					for(i=0;i<={
   fifo_addr_size{
   1'b1}};i=i+1)
						mem[i] <= {
   fifo_data_size{
   1'b0}};		//复位操作,mem初始化
				end
			else if(w_en & (~full))		//写操作，且fifo未满
				begin
					mem[w_addr] <= data_in;	//data写入mem
					w_addr <= w_addr + 1;
				end
		end
	
	//读操作
	always@(posedge clk or negedge rst)
		begin
			if(!rst)
				begin
					data_out <= {
   (fifo_data_size-1){
   1'b0}};
					r_addr <= 0;
				end
			else if(r_en & (~empty))
				begin
					data_out <= mem[r_addr];
					r_addr <= r_addr + 1;
				end
		end
		
	//count空满标志
	always@(posedge clk or negedge rst)
		begin
			if(!rst)
				begin
					count <= 0;
				end
			else  if((w_en&(~full)) & (~(r_en&(~empty))))	//写信号且非满，同时没有读操作
				count <= count + 1;
			else if((r_en&(~empty)) & (~(w_en&(~full))))	//读信号且非空，同时没有写操作
				count <= count - 1;
		end
		
	assign empty = (count == 0);
	assign full  = (count == {
   fifo_addr_size{
   1'b1}}+1);
		
endmodule

//tb
`timescale 1ns/1ns
module fifo_sync_top;
	reg clk;
	reg rst;
	reg w_en;
	reg r_en;
	reg [2:0] data_in;
	
	wire [2:0] count;
	wire [2:0] data_out;
	
	reg  [2:0] i;
	
	initial
		begin
			clk = 0;
			rst = 1;
			data_in = 3'b000;
			w_en = 0;
			r_en = 0;
			#25
			rst = 0;
			#50 
			rst = 1;
			#25
			w_en = 1;
			#100
			r_en = 1;
			#100;
			w_en = 0;
			r_en = 0;
			#100
			w_en = 1;
			#400
			r_en = 1;
		end
	
	initial
		begin
			for(i=0;i<50;i=i+1)
			#100 data_in=i;
		end
	
	always
		#50 clk = ~clk;
		
	fifo_sync #(.fifo_data_size(3), .