异步FIFO代码分析

module Asyn_FIFO(data_out, full, empty, data_in, wen, wclk, wrst,ren, rclk, rrst);

parameter datasize = 8; 
parameter addrsize = 4;

input [datasize-1:0]data_in;
input wen,ren,wclk,rclk,wrst,rrst;
output [datasize-1:0]data_out;
output empty,full;
reg empty,full;
wire [datasize-1:0]data_out;
//写指针指向下一个要被写入的单元，复位时，指向第一个单元；读指针总指向当前要被读出的数据，复位时，指向第一个单元
wire [addrsize-1:0]raddr,waddr;        
wire [addrsize:0]rbinnext,wbinnext,rptrnext,wptrnext;
wire empty_val,full_val;
reg  [addrsize:0]rbin,wbin,rptr,wptr,rptr1,rptr2,wptr1,wptr2;
reg  [datasize-1:0]memory[0:(1<<addrsize)-1];


assign data_out=memory[raddr];  //双口RAM，无条件读出，写使能并且写时钟来临才会写入
always @(posedge wclk) begin 
  if(wen&&!full) memory[waddr]<=data_in; 
end


//同步wptr指针
always @(posedge rclk or negedge rrst) begin //读时钟来临，同步写地址，用于空满检测，打两拍
 if(!rrst) {rptr2,rptr1}<=0;
      else {rptr2,rptr1}<={rptr1,wp