Notes: Hardware-based Acceleration Design 20200210

South-west Transportation University

DI Zhixiong

MOOC China from icourse163.org

https://www.icourse163.org/course/SWJTU-1207492806

 

1. Long tool line. Famous tool company: synopsis

2. Verilog HDL-hardware description language

2.1. Keypoints:

2.1.1. single `if' leads to less latency than muliple if's.

2.1.3. less `latch'.

2.1.5. share may lead to latency, therefore needs tradeoff.

2.2. style

2.2.1. complete signal list

2.2.2. no `wait' or `#delay'

2.2.3. assignement

2.3. module

2.4. summary

3. RTL

3.1. some rules

3.2. coverage related concerns

3.3. consumption