Notes: Hardware-based Acceleration Design 20200225

12 Clock Related Constraint

12.1. Clock Timing Constraint

create get_ports

set_dont_touch_network

Synthesis without clock circuit as all the rest parts are not determined and even synthesized, the clock circuit will have to be re-done later.

set_input_delay

set_output_delay

12.2. DRC constraint

set_max_transition

set_max_fanout

set_max_capacitance

13. Environment Related Constraint

13.1. set_load

13.2. Load model

14. Optimization Circuit

14.1. Overview

DRC is priory to OC.

14.2. Critical Path (group) Opt.

set a range to optimize

use `incremental'

14.3. Gate-Level Opt.

auto-ungrouping, parameter for ultra compiling

verify RTL netlist

14.4. Influence from cirtuit partitioning

Suggestions:

a) No cross partition logic

b) Register storage

=>

c) Design  the coverage according to the synthesis time

d) Separate the synchronized partition from the rest

15. TCL

15.1. Overview, Tool Commandline Language

Three components, builtin, synopsys extension and user defined.

15.2. get_* -f