Operating Conditions-工作条件

Static timing analysis is typically performed at a specific operating condition1.Anoperating condition is defined as a combination of Process, Voltage and Temperature (PVT). Cell delays and interconnect delays are computed based upon the specified operating condition.

There are three kinds of manufacturing process models that are provided by the semiconductor foundry for digital designs: slow processmodels, typical process models, and fast process models. The slow and fast process models represent the extreme corners of the manufacturing process of a foundry. For robust design, the design is validated at the extreme corners of the manufacturing process as well as environment extremes for temperature and power supply.

The choice of what operating condition to use for STA is also governed by the operating conditions under which cell libraries are available. Three standard operating conditions are:

i. WCS (Worst-Case Slow): Process is slow, temperature is highest(say 125C) and voltage is lowest (say nominal 1.2V minus 10%).For nanometer technologies that use low power supplies, there can be another worst-case slow corner that corresponds to the slow process, lowest power supply, and lowest temperature. The delays at low temperatures are not always smaller than the de-lays at higher temperatures. This is because the device threshold voltage (Vt) margin with respect to the power supply is reduced for nanometer technologies. In such cases, at low power supply,the delay of a lightly loaded cell is higher at low temperatures than at high temperatures. This is especially true of high Vt(higher threshold, larger delay) or even standard Vt (regular threshold, lower delay) cells. This anomalous behavior of delays increasing at lower temperatures is called temperature inversion.See Figure 2-23(c).

ii. TYP (Typical): Process is typical, temperature is nominal (say 25C) and voltage is nominal (say 1.2V).
iii. BCF (Best-Case Fast): Process is fast, temperature is lowest (say -40C) and voltage is highest (say nominal 1.2V plus 10%).

The static timing analysis is based on the libraries that are loaded and linked in for the STA. An operating condition for the design can be explicitly specified using the set_operating_conditions command.