前言
最近在学习一些verilog/system verilog for design的基础知识,觉得有些东西总结总结还是挺好的,毕竟好记性不如烂键盘;
正文开始
verilog有1995和2001两个标准,之后便合入到system verilog标准中了,因此结合最近看的课总结一下语法的演进;
verilog-1995
module | parameter | function | task | always @ |
assign | wire | reg | + = * / | % << >> |
$finish | $fopen | $fclose | $display | $write |
$monitor | `define | `ifdef `else `endif | `include | `timescale |
initial | disable | events | wait # | @ |
fork-join | intrger | real | time | packed array |
2D reg/memory |