知识:
门级描述,无非就是将<,>,==三个符号用门级电路来表示,然后根据行为级描述进行替换。
a == b --> ~(a^b)
a > b --> (a^b)&a
a < b --> (a^b)&b
行为级描述就是从最高位依次比较。
解法一
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output wire Y2 , //A>B
output wire Y1 , //A=B
output wire Y0 //A<B
);
assign Y1 = ~(A[0]^B[0]) & ~(A[1]^B[1]) & ~(A[2]^B[2]) & ~(A[3]^B[3]);
assign Y2 = ((A[3]^B[3])&A[3]) |
(~(A[3]^B[3]) & ((A[2]^B[2])&A[2])) |
(~(A[3]^B[3]) & ~(A[2]^B[2]) & ((A[1]^B[1])&A[1])) |
(~(A[3]^B[3]) & ~(A[2]^B[2]) & ~(A[1]^B[1]) & ((A[0]^B[0])&A[0]));
assign Y0 = ((A[3]^B[3])&B[3]) |
(~(A[3]^B[3]) & ((A[2]^B[2])&B[2])) |
(~(A[3]^B[3]) & ~(A[2]^B[2]) & ((A[1]^B[1])&B[1])) |
(~(A[3]^B[3]) & ~(A[2]^B[2]) & ~(A[1]^B[1]) & ((A[0]^B[0])&B[0]));
endmodule
解法二:转换为门电路
a>b --- a&(~b)
a<b --- (~a)&b
a=b ---~a^b
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output wire Y2 , //A>B
output wire Y1 , //A=B
output wire Y0 //A<B
);
assign Y2 = (A[3]&(~B[3]))|(~A[3]^B[3])&(A[2]&(~B[2]))|(~A[3]^B[3])&(~A[2]^B[2])&(A[1]&(~B[1]))|(~A[3]^B[3])&(~A[2]^B[2])&(~A[1]^B[1])&(A[0]&(~B[0]));
assign Y1 = (~A[3]^B[3])&(~A[2]^B[2])&(~A[1]^B[1])&(~A[0]^B[0]);
assign Y0 = ((~A[3])&B[3])|(~A[3]^B[3])&((~A[2])&B[2])|(~A[3]^B[3])&(~A[2]^B[2])&((~A[1])&B[1])|(~A[3]^B[3])&(~A[2]^B[2])&(~A[1]^B[1])&((~A[0])&B[0]);
endmodule
解法三:最容易想到的
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output reg Y2 , //A>B
output reg Y1 , //A=B
output reg Y0 //A<B
);
always @(*) begin
if(A==B) begin
Y0 = 0;
Y1 = 1;
Y2 = 0;
end
else if(A[3]>B[3]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[3]<B[3]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[2]>B[2]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[2]<B[2]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[1]>B[1]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
if(A[1]<B[1]) begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
else begin
if(A[0]>B[0]) begin
Y0 = 0;
Y1 = 0;
Y2 = 1;
end
else begin
Y0 = 1;
Y1 = 0;
Y2 = 0;
end
end
end
end
end
end
end
end
endmodule
解法四:自己写的
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output reg Y2 , //A>B
output reg Y1 , //A=B
output reg Y0 //A<B
);
always@(A or B)
begin
if(A[3]>B[3])begin
Y2=1;
Y1=0;
Y0=0;
end
else if(A[3]>B[3])begin
Y2=0;
Y1=0;
Y0=1;
end
else if((A[3]==B[3])&&(A[2]>B[2]))begin
Y2=1;
Y1=0;
Y0=0;
end
else if((A[3]==B[3])&&(A[2]<B[2]))begin
Y2=0;
Y1=0;
Y0=1;
end
else if((A[3]==B[3])&&(A[2]==B[2])&&(A[1]>B[1]))begin
Y2=1;
Y1=0;
Y0=0;
end
else if((A[3]==B[3])&&(A[2]==B[2])&&(A[1]<B[1]))begin
Y2=0;
Y1=0;
Y0=1;
end
else if((A[3]==B[3])&&(A[2]==B[2])&&(A[1]==B[1])&&(A[0]>B[0]))begin
Y2=1;
Y1=0;
Y0=0;
end
else if((A[3]==B[3])&&(A[2]==B[2])&&(A[1]==B[1])&&(A[0]<B[0]))begin
Y2=0;
Y1=0;
Y0=1;
end
else if((A[3]==B[3])&&(A[2]==B[2])&&(A[1]==B[1])&&(A[0]==B[0]))begin
Y2=0;
Y1=1;
Y0=0;
end
end
endmodule
解法五:直接比较整体
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output wire Y2 , //A>B
output wire Y1 , //A=B
output wire Y0 //A<B
);
assign Y2 = (A>B)?1:0;
assign Y1 = (A==B)?1:0;
assign Y0 = (A<B)?1:0;
endmodule
解法六
`timescale 1ns/1ns
module comparator_4(
input [3:0] A ,
input [3:0] B ,
output wire Y2 , //A>B
output wire Y1 , //A=B
output wire Y0 //A<B
);
assign Y2 = (A[3]>B[3]) + (A[3]==B[3]&&A[2]>B[2]) + (A[3]==B[3]&&A[2]==B[2]&&A[1]>B[1]) + (A[3]==B[3]&&A[2]==B[2]&&A[1]==B[1]&&A[0]>B[0]);
assign Y1 = A[3]==B[3]&&A[2]==B[2]&&A[1]==B[1]&&A[0]==B[0];
assign Y0 = (A[3]<B[3]) + (A[3]==B[3]&&A[2]<B[2]) + (A[3]==B[3]&&A[2]==B[2]&&A[1]<B[1]) + (A[3]==B[3]&&A[2]==B[2]&&A[1]==B[1]&&A[0]<B[0]);
endmodule