思路:主要理清题目思路就好做了,分析题目的每个变量的含义以及相互联系。ready_a在代码中一直拉高,valid_a=1,data_a此时有效,且数据拼接时先接收到的数据放到data_b的低位。所以data_a放在高位。在cnt计数到5时valid_b有效,否则一直计数.
解法一
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
); reg[5:0] b;
reg[5:0] cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_b<=0;
valid_b<=0;
cnt<=0;
ready_a<=0;
b<=0;
end
else
ready_a<=1;
if(valid_a)begin
b<={data_a,b[5:1]};
if(cnt==5)begin
cnt<=0;
valid_b<=1;
data_b<={data_a,b[5:1]};
end
else begin
valid_b<=0;
cnt<=cnt+1;
end
end
end
endmodule
解法二
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [5:0] data_reg;
reg [2:0] data_cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
ready_a <= 0;
else
ready_a <= 1'd1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_cnt <= 3'd0;
else if(valid_a && ready_a)
data_cnt <= (data_cnt == 3'd5) ? 3'd0 : (data_cnt + 3'd1);
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_reg <= 6'd0;
else if(valid_a && ready_a)
data_reg <= {data_a,data_reg[5:1]};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
valid_b <= 0;
data_b <= 6'd0;
end
else if(data_cnt == 3'd5)begin
valid_b <= 1'd1;
data_b <= {data_a,data_reg[5:1]};
end
else
valid_b <= 1'd0;
end
endmodule
解法三:意义不大
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] shift_reg;
reg first_rst;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 3'd0;
else if(valid_a && cnt == 3'd5)
cnt <= 3'd0;
else if(valid_a)
cnt <= cnt + 3'd1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
shift_reg <= 6'd0;
else if(valid_a)
shift_reg <= {data_a,shift_reg[5:1]};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_b <= 6'd0;
else if(cnt == 3'd5)
data_b <= {data_a,shift_reg[5:1]};
else
data_b <= data_b;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
valid_b <= 1'b0;
else if(cnt == 3'd5)
valid_b <= 1'b1;
else
valid_b <= 1'b0;
end
initial begin
ready_a = 1'b0;
end
always@(posedge clk)begin
ready_a <= rst_n | ready_a;
end
endmodule
解法四
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [5:0] data_bb;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
ready_a <= 1'b0;
valid_b <= 1'b0;
data_bb <= 6'b0;
data_b <= 6'b0;
cnt <= 3'b0;
end
else begin
ready_a <= 1'b1;
if(valid_a)begin
data_bb <= {data_a,data_bb[5:1]};
if(cnt == 3'd5)begin
cnt <= 3'd0;
valid_b <= 1'b1;
data_b <= {data_a,data_bb[5:1]};
end
else begin
cnt <= cnt + 3'b1;
valid_b <= 1'b0;
end
end
else begin
data_bb <= data_bb;
valid_b <= valid_b;
end
end
end
endmodule