xilinx错误集锦

xilinx  ISE使用错误和警告

  (2012-03-22 15:46:49)

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（1）编dcm时钟控制测试程序时，设置好了ip，例化输出，综合时出现错误
ERROR:Xst:2035 - Port <clk> has illegal connections. This port is connected to an input buffer and other components.
   查到的解决方法是禁掉自动I/O Buffer insertion 功能，具体的做法是右击synthesize，然后properties->Xilinx Specific Options,把add I/O buffer 的勾去掉，综合通过。但是这样处理了之后在map时又引入了许多的warning，而且还会引发错误。方法出处一会转帖出来。
（2）dac8812的控制时序测试时，综合没问题，但是map时出现错误
   Pack:198 - NCD was not produced. All logic was removed from design.
   其实这个错误的来源是下面的这几个warning导致
   MapLib:701 - Signal clk connected to top level port clk has been removed.
MapLib:701 - Signal dad connected to top level port dad has been removed.
   以下省略很多这样的warning，这个问题之前一直没注意，后来才知道问题出在我在问题（1）中的处理，按照同样的流程把add I/O buffer 勾上，综合到route都没什么问题，可见warning也是不能忽略的呀。
（3）刚才不知道怎么了，行为仿真的时候出现下面的error
   ERROR:HDLParsers:3482 - Could not resolve instantiated unit dacinter in Verilog module work/datest_top in any library
   意思好像是找不到我top里例化的模块了，重新添加了一下，好用了。
（4）行为仿真发现没有波形，全是XX或者ZZZ，以前改一下clk频率就好了，这回这招不好使了，后来尝试改了一下rst的时间点，向后一段时间，发现好用了，仿真用的是ise自带的simulation。
（5）综合错误：ERROR:Xst:528 - Multi-source in Unit <entity> on signal <sig>
   大多数时候应该是同一个变量，在两个always模块中赋值了。还查到一些其他情况，一并粘贴：
Solution 1
This error appears when XST determines that there is contention on a particular signal. If the processes assigning values to this signal are mutually exclusive (as in the case of 3-state buffers), this message can be ignored.
However, in most cases, XST is able to determine when multiple drivers are illegal, and will stop synthesis soon after this message.
Check this signal and modify your code to avoid the existing contention. 
Solution 2
In some cases, XST ties unconnected output ports to ground. If the output port is part of a 3-state bus, which in turn connects to another 3-state bus, then connecting one bit of the bus to ground will cause a multiple-driver error. Verify that this is not occurring in your design by searching for the following warning:
"WARNING:Xst:1305 - Output <dataout<23>> is never assigned. Tied to value 0."
To work around this issue, remove the unused output port. 
Solution 3
This has also been seen in the following condition: 
When there is an association signal named to_qvm_d4.Q_num.
When using association signal(to_qvm_d4.Q_num), XST will rename it to "to_qvm_d4_Q_num" during synthesis. There is signal named "to_qvm_d4_Q_num" in the same architecture. XST is confused with these two signals and errors.
To work around this issue, rename either of the two signals. 
Solution 4
EDK Designs
For EDK Designs using bidirectional signals DIR=IO and THREE_STATE=FALSE, the external port name must match the connecting signal name exactly. NOTE: IOB_STATE is deprecated in future EDK versions.
（6）ERROR:Xst:902 - "dec_seg.v" line 38: Unexpected event in always block sensitivity list.
一个组合电路，综合出错，上网查说是敏感表中不能既有电平又有边沿，而且也不能同一个信号的上升沿和下降沿同时出现，去掉敏感表中的边沿，运行OK了。
（7）map的时候出现错误ERROR:Pack:679 - Unable to obey design constraints (LOC = ...) which require the combination of the following symbols into a single slice component:
检查ucf文件，发现有一个管脚被重复分配，改了一下，运行OK！
（8）ERROR:NgdBuild:604 - 'GTP_DUAL_1' could not be resolved，这个错误在translate的时候报，是软件的bug，网上查说ise12.2多发，但是我用的9.1也出了这个，原因大概是ISE只复制了顶层的NGC文件，即mycpu.ngc，而顶层mycpu还包含其它ngc文件，因此找不到，报错。按照查到的解决办法，有两种。 
解决办法1是：在mycpu module前面加上
(* box_type = "user_black_box" *)
如：
(* box_type = "user_black_box" *)
mycpu my_cpu_moudle (.fpga_0_clk_1_sys_clk_pin(sys_clk),
.fpga_0_rst_1_sys_rst_pin(sys_rst_n),
.fpga_0_RS232_RX_pin(uart_rxd),
.fpga_0_RS232_TX_pin(uart_txd),
   .led_out_GPIO_IO_O_pin(led_out[0:3]));
办法2是在ISE 的processes栏下，选中Translate，右键process propreties.....
弹出Translate Properties对话框，
在-sd macro search path 中加上EDK工程的implementation子目录的路径就可以了
一开始采用了第一种解决方案，translate通过，但在map时出错。改用第二种，问题是，我用了两个ip core，这个指定的路径只能是一个最直接的目录，所以只能完全解决其中一个core的错误，把两个core的文件夹里的文件全拷到工程目录中，指定工程目录路径为implementation子目录路径，搞定。

可以忽略的warning
（1）ProjectMgmt - "F:/verilogworks/FPGATESTS/datest_top_map.ncd" line 0 duplicate design unit: 'Module|datest_top'