实验要求:
采用ise软件,verlog语言,最后用modelsim仿真。 输入异步复位rst_n,使能端口ce_i,控制加减ctr_i,输入时钟信号clk;输出为4为位宽的d_out,实现0到15的不断计数,并且可由ctr_i控制计数的加减;
实验代码
module new_rev(
input clk_i,
input rst_i, //复位按键
input ce_i, //使能
input ctr_i, //控制加减
output [3:0] d_out
);
reg[3:0]counter=0;
assign d_out=counter;
always@(posedge clk_i or posedge rst_i)
if(rst_i==1) //复位
begin
counter<=0;
end
else
if(ce_i==0) //使能
begin
counter<=counter;
end
else //控制加减
if(ctr_i==1)
case(counter)
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15:begin
if(counter==15)
counter<=0;
else counter<=counter+1;
end
endcase
else
case(counter)
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15: begin
if(counter==0)
counter<=15;
else
counter<=counter-1;
end
endcase
endmodule
测试文件
module sssss;
// Inputs
reg clk_i;
reg rst_i;
reg ce_i;
reg ctr_i;
// Outputs
wire [3:0] d_out;
// Instantiate the Unit Under Test (UUT)
new_rev uut (
.clk_i(clk_i),
.rst_i(rst_i),
.ce_i(ce_i),
.ctr_i(ctr_i),
.d_out(d_out)
);
initial begin
// Initialize Inputs
clk_i = 0;
rst_i = 0;
ce_i = 0;
ctr_i = 0;
// Wait 100 ns for global reset to finish
#25;
rst_i = 0; //复位信号为低电平,正常计数
ce_i = 1;
ctr_i = 1;
#200; //复位信号为高
rst_i = 1;
ce_i = 1;
ctr_i = 1;
#25; //继续正常加
rst_i = 0;
ce_i = 1;
ctr_i = 1;
#100;
rst_i = 0; //使能端口关闭,计数停止,保持当前数值
ce_i = 0;
ctr_i = 1;
#50;
rst_i = 0; //使能端口开启,计数继续
ce_i = 1;
ctr_i = 1;
#100;
rst_i = 0; //计数减
ce_i = 1;
ctr_i = 0;
// Add stimulus here
end
always#5 clk_i=~clk_i;
endmodule