题目
代码
module top_module (input x, input y, output z);
wire out1,out2,out3,out4,out5,out6;
A IA1(x,y,out1);
A IA2(x,y,out3);
B IB1(x,y,out2);
B IB2(x,y,out4);
assign out5=out1|out2;
assign out6=out3&out4;
assign z=out5^out6;
endmodule
module A (input x,input y,output z);
assign z = (x^y) & x;
endmodule
module B (input x,input y,output z);
assign z = ~x^y;
endmodule