0×02:FPGA设计思想

well, it seems that I have a long way to go~
这几天敲FPGA的代码，发现很多问题，于是回来看书，以下是笔记。
还是Advanced FPGA Design: Architecture, Implementation, and Optimization
不过这次主要是一些顶层设计思想、时钟同步和复位的问题。

顶层优化设计：

抽象状态机
Graphical state machines are much easier to read and allow for automatic
speed/area optimizations.

Of key importance is the readability of the top level of abstraction where
the design takes place. Of less importance is the readability of the
autogenerated RTL.

DSP设计：
Some abstract design tools such as Synplify DSP allow for automatic architectural
trade-off such as pipelined versus folded implementations.

时域分析：
Clock synchronization issues are generally not repeatable and will affect the
reliability of the FPGA design.

时钟的亚稳态：
Metastability can cause catastrophic failfures in the FPGA.

亚稳态解决方案1：phase control
The phase-control technique can be used when the period of one clock is a multiple
of the other and when one of the clocks can be controlled by an internal PLL or DLL
文中说这种方法仅限于时序要求高但时钟由外部输入或者两个时钟没有关系的情况。
如果是FPGA为两个系统提供时序约束的情况，phase control失效。

亚稳态解决方案2：double flopping
Double flopping can be used to resynchronize single-bit signals between two
asynchronous clock domains.
两个触发器之间的时序必须减到最小，这样才能降低第二个时钟出现亚稳态的可能性。
TIming analysis should ignore the first resynchronization flip-flop and ensure that
the timing between the synchronization flip-flops themselves is minimized.

亚稳态解决方案3：使用FIFO
FIFOs can be used when passing multibit signals between asynchronous clock
domains.
但是必须控制fifo，握手协议+防止溢出。

Gray codes can be used to pass multibit counter data between asynchronous clock
domains and are often used inside FIFOs.

Synchronization register should be partitioned as independent blocks outside of
the functional modules.

ASIC原型中的gated clocks

启用时钟模块
Avoid clock gating.Keep all gated clocks inside a dedicated clocks module and
separate from the functional modules.

复位电路

Reset recovery time violations occur at the deassertion of reset. and fully
asynchronous resets are NOT recommended.

Fully synchronous resets may fail to capture the reset signal itself depending
on the nature of the clock. So fully synchronous resets are NOT recommended.

A reset circuit that asserts asynchronously and deasserts synchronously
generally provides a more reliable reset than fully synchronous or fully
asynchronous resets.

Different reset types should not be used in a single always block.

A separate reset synchronizer must be used for each independent clock domain.