牛客网VL63--并串转换

1.先用寄存器存储输入的数据

2.进行左移1位

3.用计数器计数，4个周期后，输出valid_in高，输出寄存器最高位

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
reg [3:0] data;
reg [1:0] cnt;
reg valid;

always@(posedge clk or negedge rst) begin
	if(!rst)
		cnt <= 0;
	else
		cnt <= cnt + 1;

end

always@(posedge clk or negedge rst) begin
	if(!rst) begin
		data <= 4'b0;
		valid <= 1'b0;
	end
	else if(cnt == 3) begin
		valid <= 1'b1;
		data <= d;
	end
	else begin
		valid <= 1'b0;
		data <= data << 1;
	end
end


assign valid_in = valid;
assign dout = data[3];





//*************code***********//

endmodule