DC -.sdc & .sdf

SDC - Synopsys Design Constraints
This file is used for all implementation tools starting from synthesis, timing analysis, place&route,dft,fpga…etc. This is very important file to ensure proper operation of your design, fpga, silicon

SDF - Standard Delay Format
Used to convey the timing information of a design after implementation (it can be generated at all of above steps). This is what says whats the delay at each cell, net, node. This is exported to do the simulation of design and to find if the design is operating at the Frequency without any setup/hold violations.