最简单VCS工程，加法器测试

该工程包括：full_adder.v、full_adder_tb.v、timescale.v和Makefile四个文件。https://github.com/leoicer/prj_verify/tree/main/eecourse/lab1_full_adder

//full_adder.v
module full_adder(
	input wire a_in,
	input wire b_in,
	input wire c_in,
	output wire sum_out,
	output wire c_out
);

assign {
   c_out,sum_out} = a_in + b_in + c_in;
endmodule

//full_adder_tb.v
module full_adder_tb;

reg  ain, bin, cin;
wire sumout, cout;

full_adder u_full_adder(
    .a_in(ain),
	.b_in(bin),
	.c_in(cin),
	.sum_out(sumout),
	.c_out(cout)
);

//task2: clk and rst generator
parameter  CLK_PERIOD = 20;

reg clk, reset_n;

initial begin
        clk = 0;
    forever begin
        #CLK_PERIOD clk = ~clk;                
    end
end

initial begin
    reset_n = 0;
    #100 
    reset_n =