verilog 笔试题

一道verilog笔试题

博主好久没写博客，最近看到一个校招笔试题，就随手写了。下面是题目

verilog code

`timescale 1ns / 1ps
//
// Company: 
// Engineer: zhangsy
// 
// Create Date: 2019/11/22 12:58:44
// Design Name: 
// Module Name: signal
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module signal(
                input clk,
                input  rst,
                input  Signal1,
                output reg   out1,   
                output reg   out2,   
                output reg   out3   
);    
reg [3:0] count;
reg flag;
always @ (posedge clk )
    if(rst)
        begin
            count <= 4'd0;
        end
    else if(count =