verilog面试题

1.
Use verilog hdl to implement a flip-flopwith synchronous RESET and SET, a Flip-flop with asynchronous RESET and SET.
实现同步置位和复位的触发器。实现异步置位和复位的触发器。

always@(posedgeclk or negtive set or negtive reset)

if(set)

q<=1;

elseif (!reset)

q<=0;


else

q<=d;

2.
Use verilog hdl to implement a latch withasynchronous RESET and SET.

实现异步置位和复位的锁存器。

always@(clk or set orreset)

if(set)

q<=1;

elseif (!reset)

q<=0;

else

q<=d;


3.
Use Verilog hdl to implement a 2-to-1multiplexer.
实现二选一。

assignout = sel? a:b;

4.
Use AND gate, OR gate and Inverter toimplement a 2-to-1 multiplexer.
用门级电路搭二选一。
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5.
Use a 2-to-1 multiplexer to implement a twoinput OR gate.

用二选一搭或门。

assign out = a? a:b ;
6.
Use a tri-state buffer to implementOpen-Drain buffer.

用三态实现开路。

Assign out = en? In: 1’bz ;

7.
To divide one input clock by3, Written byverilog hdl.

三分频。


8.
To divide one input clock by3, 50% dutycycle is required. Written by verilog hdl.

三分频，50％空占比。

The 7 and 8 is basic same. I give the 8answer.

`timescale 1ns / 1ps

module diveven;

reg rst;
reg clkin;
wire clkout;
regclkout1,clkout2;
reg [2:0] count;

always #50 clkin =~clkin;

initial

begin

clkin = 0;

rst = 1;

#200 rst = 0;


end


assign clkout =clkout1 | clkout2;

always@(posedgeclkin)
if(rst)

begin

count <= 0;

end 
else if(count ==3'h2)

begin


count<=0;

end
else

count <= count+1;

always@(posedgeclkin)
if(rst)

begin

clkout1 <= 0;

end 
else if(count ==3'h2)

begin


clkout1<=~clkout1;

end
else if(count ==3'h1)


begin


clkout1<=~clkout1;

end



always@(negedgeclkin)
if(rst)

begin

clkout2 <= 0;

end 
else if(count ==3'h2)

begin


clkout2<=~clkout2;


end
else if(count ==3'h1)


begin


clkout2<=~clkout2;

end


endmodule

9.
Pickup any interface from the following.Draw the waveform and block diagram. Writhe the verilog code for serial toparallel data conversion.

从下面串口中挑选一个你熟悉的，画框图和波形。并写一段串转并的程序。

UART, SPI, PS2, LPC, USB, I2C, I2S, SATA, MMC, SD


always(posedge clk)

begin

rsr[0]<= rxd;

rsr[7:1]<= rsr[6:0];

end

assignout <= rsr;