FPGA三人表决器问题总结

最新推荐文章于 2024-06-23 20:10:28 发布

qq_27041091

最新推荐文章于 2024-06-23 20:10:28 发布

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文章标签： FPGA

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1.所有信号都显示为高阻态,是语法问题造成的,一定要注意下面的ERROR信息.此次为$stop后面未加分号

`timescale 1 ps/ 1 ps
module Project_Vote1_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg A;
reg B;
reg C;
// wires                                               
wire L;

// assign statements (if any)                          
Project_Vote1 i1 (
// port map - connection between master ports and signals/registers   
	.A(A),
	.B(B),
	.C(C),
	.L(L)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
$monitor($time,"Y value = %b\n",L); 
//激励信号产生 
A = 1'b0;B = 1'b0;C = 1'b0;
//等待1000ps=1ns
#1000;A = 1'b0;B = 1'b0;C = 1'b1;
#1000;A = 1'b0;B = 1'b1;C = 1'b0;
#1000;A = 1'b0;B = 1'b1;C = 1'b1;
#1000;A = 1'b1;B = 1'b0;C = 1'b0;
#1000;A = 1'b1;B = 1'b0;C = 1'b1;
#1000;A = 1'b1;B = 1'b1;C = 1'b0;
#1000;A = 1'b1;B = 1'b1;C = 1'b1;


#1000;

$stop;
                                                                                                                    
end                                                                                                 
endmodule