参考:
ZYNQ UltraScale+ MPSoC OpenAMP 2019.1官网资料翻译
ZYNQ UltraScale+ MPSoC OpenAMP 2018.3官网资料翻译
官网资料
MPSOC运行两个R5裸机与运行单个裸机程序相似
Zynq UltraScale+ MPSoC 在linux系统运行R5 裸机程序 remoteproc - R5
设备树修改
设备树可以参考
kernel-source\Documentation\devicetree\bindings\remoteproc\xilinx,zynqmp-r5-remoteproc.yaml
和kernel-source\Documentation\devicetree\bindings\remoteproc\xilinx,zynqmp-r5-remoteproc.txt
两个文件
预留两块内存给R5_0 和R5_1两个裸机运行,预留共享内存方便不同核之间进行信息交互
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rproc_0_reserved: rproc@0x42000000 {
no-map;
reg = <0x0 0x42000000 0x0 0x1000000>;
};
rproc_1_reserved: rproc@0x44000000 {
no-map;
reg = <0x0 0x44000000 0x0 0x1000000>;
};
share_memory: r5sh_mem@0x64000000 {
no-map;
reg = <0x0 0x64000000 0x0 0x1000000>;
};
};
分别配置
tcm_0a tcm_0b 引导R5_0
tcm_1a tcm_1b 引导R5_1
两个RPU寄存器地址范围分别为
reg = <0x0 0xFF9A0100 0x0 0x100>;
reg = <0x0 0xFF9A0200 0x0 0x100>;
注意size是0x100。参考文件
power-domain分别为7 和 8 参考zynqmp_r5_remoteproc.c文件中power-domain属性。
ret = of_property_read_u32(node, “power-domain”, &(*z_rproc)->pnode_id);
VERSAL_RPU_0,VERSAL_RPU_1宏定义已经定好。
power-domain = <0x7>;
power-domain = <0x8>;
如果R5_0 R5_1只是运行内存地址不同,tcm,reg,power-domain没有区分开,无法同时运行两个R5程序,只能同一时间运行一个裸机。
/* IPI device */
ipi_amp: ipi@ff340000 {
compatible = "ipi_uio";
reg = <0x0 0xff340000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
};
tcm_0a@ffe00000 {
no-map;
reg = <0x0 0xffe00000 0x0 0x10000>;
phandle = <0x40>;
status = "okay";
compatible = "mmio-sram";
};
tcm_0b@ffe20000 {
no-map;
reg = <0x0 0xffe20000 0x0 0x10000>;
phandle = <0x41>;
status = "okay";
compatible = "mmio-sram";
};
tcm_1a@0xffe90000 {
no-map;
reg = <0x0 0xffe90000 0x0 0x10000>;
phandle = <0x42>;
status = "okay";
compatible = "mmio-sram";
};
tcm_1b@0xffeb0000 {
no-map;
reg = <0x0 0xffeb0000 0x0 0x10000>;
phandle = <0x43>;
status = "okay";
compatible = "mmio-sram";
};
zynqmp-rpu {
compatible = "xlnx,zynqmp-r5-remoteproc";
xlnx,cluster-mode = <1>;
ranges;
reg = <0x0 0xFF9A0000 0x0 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
r5_0: r5@0 {
compatible = "xilinx,r5f";
reg = <0x0 0xFF9A0100 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sram = <0x40 0x41>;
memory-region = <&rproc_0_reserved>;
power-domain = <0x7>;
};
r5_1: r5@1 {
compatible = "xilinx,r5f";
reg = <0x0 0xFF9A0200 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sram = <0x42 0x43>;
memory-region = <&rproc_1_reserved>;
power-domain = <0x8>;
};
};
vitis裸机程序需要分别新建R5_0 和 R5_1的裸机程序,修改lscript.ld的ddr地址,分别对应rproc_0_reserved和rproc_1_reserved。