西电计科大三下SOC微体系结构设计实验合集

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目录

二.线下实验

管脚绑定模版

通用模块模版

注意事项

1.跑马灯控制设计

2.8 位并行全加器设计+数码管显示程序设计

3.阵列乘法器设计

4.先进先出 FIFO 的设计

5.PC 程序计数器设计

6.程序存储器 ROM 设计

7.加减交替除法器

8.指令存储器 IR 设计

9.寄存器 RN 设计

10.ALU算术逻辑单元设计

11.数据存储器 RAM 设计

12.堆栈指针 SP 设计

13.采用硬件描述语言语言设计 IO 模块

14.微控制器设计

15.8 位 SOC 综合设计

1.实验结果分析

<1>模块工作顺序分析

<2>​​​指令执行过程分析

2.其他

<1>SOC模块集成设计经验

<2>SOC集成关键


二.线下实验

管脚绑定模版

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/18 13:02:24
#----------------------------------------------------------------------------------
#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]

#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {a_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {a_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {a_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {a_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {a_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {a_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {a_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {a_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {a_in[7]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {b_in[7]}]
set_property PACKAGE_PIN B10        [get_ports {b_in[0]}]
set_property PACKAGE_PIN A10        [get_ports {b_in[1]}]
set_property PACKAGE_PIN B15        [get_ports {b_in[2]}]
set_property PACKAGE_PIN A15        [get_ports {b_in[3]}]
set_property PACKAGE_PIN A13        [get_ports {b_in[4]}]
set_property PACKAGE_PIN A12        [get_ports {b_in[5]}]
set_property PACKAGE_PIN D8         [get_ports {b_in[6]}]
set_property PACKAGE_PIN D9         [get_ports {b_in[7]}]

#SW16~23
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {c_in[7]}]
set_property PACKAGE_PIN F8         [get_ports {c_in[0]}]
set_property PACKAGE_PIN F9         [get_ports {c_in[1]}]
set_property PACKAGE_PIN H11        [get_ports {c_in[2]}]
set_property PACKAGE_PIN H12        [get_ports {c_in[3]}]
set_property PACKAGE_PIN G14        [get_ports {c_in[4]}]
set_property PACKAGE_PIN J10        [get_ports {c_in[5]}]
set_property PACKAGE_PIN H14        [get_ports {c_in[6]}]
set_property PACKAGE_PIN J11        [get_ports {c_in[7]}]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports rst]
set_property IOSTANDARD LVCMOS18    [get_ports rst]
set_property PACKAGE_PIN J14        [get_ports key_in]
set_property IOSTANDARD LVCMOS18    [get_ports key_in]
set_property PACKAGE_PIN H9         [get_ports wr]
set_property IOSTANDARD LVCMOS18    [get_ports wr]
set_property PACKAGE_PIN H8         [get_ports rd]
set_property IOSTANDARD LVCMOS18    [get_ports rd]
set_property PACKAGE_PIN G10        [get_ports a]
set_property IOSTANDARD LVCMOS18    [get_ports a]
set_property PACKAGE_PIN G9         [get_ports b]
set_property IOSTANDARD LVCMOS18    [get_ports b]
set_property PACKAGE_PIN J13        [get_ports c]
set_property IOSTANDARD LVCMOS18    [get_ports c]
set_property PACKAGE_PIN H13        [get_ports d]
set_property IOSTANDARD LVCMOS18    [get_ports d]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

#LED
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[6]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[7]}]
set_property PACKAGE_PIN G16			[get_ports {data_out[0]}]
set_property PACKAGE_PIN H16 			[get_ports {data_out[1]}]
set_property PACKAGE_PIN D16 			[get_ports {data_out[2]}]
set_property PACKAGE_PIN D15 			[get_ports {data_out[3]}]
set_property PACKAGE_PIN C18 			[get_ports {data_out[4]}]
set_property PACKAGE_PIN C17 			[get_ports {data_out[5]}]
set_property PACKAGE_PIN B19 			[get_ports {data_out[6]}]
set_property PACKAGE_PIN C19 			[get_ports {data_out[7]}]

#led15
set_property PACKAGE_PIN L20        [get_ports empty]
set_property IOSTANDARD LVCMOS33    [get_ports empty]
#led11
set_property PACKAGE_PIN J20        [get_ports full]
set_property IOSTANDARD LVCMOS33    [get_ports full]

通用模块模版

时钟分频:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk_div is
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end clk_div;

architecture Behavioral of clk_div is

begin

process(rst,clk_in)
variable count:integer:=0;
begin
    if(rst='1')then count:=0; 
    elsif(clk_in='1'and clk_in'event)then 
        count:=count+1;
        if(count<=DIV_NUM/2)then
            clk_out<='1';
        elsif(count>DIV_NUM/2 and count<DIV_NUM)then
            clk_out<='0';
        elsif(count>=DIV_NUM)then
            count:=0;
        end if;
    end if;
end process;

end Behavioral;

按键消抖:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity key_stroke is
    generic(CLK_FRE:integer:=100000000);
    Port (
        clk:in std_logic;
        reset:in std_logic;
        key_in:in std_logic;
        output:out std_logic           
    );
end key_stroke;

architecture Behavioral of key_stroke is

type states is(s0,s1,s2,s3);
signal state:states;

begin

process(reset,clk,key_in)
variable count_num:integer:=3*CLK_FRE/1000;--delay 3ms
variable count:integer:=0;
    begin
        if reset='0'then
            state<=s0;
            count:=0;
            output<='0';
        elsif(clk='1'and clk'event)then
            case state is
                when s0=>if(key_in='1')then count:=0;output<='0';state<=s1;end if;
                when s1=>
                    count:=count+1;
                    if (count>=count_num) then state<=s2; end if;
                when s2=>
                    if(key_in='1')then output<='1';state<=s3;
                    --if(key_in='1')then output<='1';state<=s0;--one clk cycle
                    elsif(key_in='0')then state<=s0;
                    end if;
                when s3=>if(key_in='0')then state<=s0;end if;                                                                   
            end case;               
        end if;     
end process;

end Behavioral;

 数码管显示:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seg_dis is
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );

end seg_dis;

architecture Behavioral of seg_dis is

signal data_in_line: std_logic_vector(3 downto 0);

type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal state,next_state:states;

begin   

process(rst,clk)
begin 
    if(rst='1')then state<=s0;
    elsif(clk='1'and clk'event)then 
        state<=next_state;
    end if;
end process;


process(state)
begin
    case state is
    when s0 =>  seg_dig<=not"0000000000000001";   data_in_line<=data_in_A(3 downto 0);   next_state<=s1;
    when s1 =>  seg_dig<=not"0000000000000010";   data_in_line<=data_in_A(7 downto 4);   next_state<=s2;
    when s2 =>  seg_dig<=not"0000000000000100";   data_in_line<=data_in_A(11 downto 8);  next_state<=s3;
    when s3 =>  seg_dig<=not"0000000000001000";   data_in_line<=data_in_A(15 downto 12); next_state<=s4;   
    when s4 =>  seg_dig<=not"0000000000010000";   data_in_line<=data_in_B(3 downto 0);   next_state<=s5;
    when s5 =>  seg_dig<=not"0000000000100000";   data_in_line<=data_in_B(7 downto 4);   next_state<=s6;
    when s6 =>  seg_dig<=not"0000000001000000";   data_in_line<=data_in_B(11 downto 8);  next_state<=s7;
    when s7 =>  seg_dig<=not"0000000010000000";   data_in_line<=data_in_B(15 downto 12); next_state<=s8;     
    when s8 =>  seg_dig<=not"0000000100000000";   data_in_line<=data_in_C(3 downto 0);   next_state<=s9;
    when s9 =>  seg_dig<=not"0000001000000000";   data_in_line<=data_in_C(7 downto 4);   next_state<=s10;
    when s10=>  seg_dig<=not"0000010000000000";   data_in_line<=data_in_C(11 downto 8);  next_state<=s11;
    when s11=>  seg_dig<=not"0000100000000000";   data_in_line<=data_in_C(15 downto 12); next_state<=s12;
    when s12=>  seg_dig<=not"0001000000000000";   data_in_line<=data_in_D(3 downto 0);   next_state<=s13;
    when s13=>  seg_dig<=not"0010000000000000";   data_in_line<=data_in_D(7 downto 4);   next_state<=s14;
    when s14=>  seg_dig<=not"0100000000000000";   data_in_line<=data_in_D(11 downto 8);  next_state<=s15;
    when s15=>  seg_dig<=not"1000000000000000";   data_in_line<=data_in_D(15 downto 12); next_state<=s0;
    when others=>next_state<=s0;
    end case;
end process;

process(data_in_line)
begin
    case data_in_line is
        when "0000"=>seg_data<=not"00111111";
        when "0001"=>seg_data<=not"00000110";
        when "0010"=>seg_data<=not"01011011";
        when "0011"=>seg_data<=not"01001111";
        when "0100"=>seg_data<=not"01100110";
        when "0101"=>seg_data<=not"01101101";
        when "0110"=>seg_data<=not"01111101";
        when "0111"=>seg_data<=not"00000111";
        when "1000"=>seg_data<=not"01111111";
        when "1001"=>seg_data<=not"01101111";
        when "1010"=>seg_data<=not"01110111";
        when "1011"=>seg_data<=not"01111100";
        when "1100"=>seg_data<=not"00111001";
        when "1101"=>seg_data<=not"01011110";
        when "1110"=>seg_data<=not"01111001";
        when "1111"=>seg_data<=not"01110001";
        when others=>seg_data<=not"11111111";
    end case;
end process;

end Behavioral;

注意事项

1.器件型号:xc7k160tfbg676-2

2.输入一般cmos18 输出cmos33

3.输入数码管的时钟需分频

4.按键加消抖

5.程序的运行结合.xdc文件进行理解

1.跑马灯控制设计

        功能叙述:初始情况下 Y0=‘1’,其它为‘0’。然后,在 en 为高电平的情况下,在时钟信 号 clk 的下降沿进行移位。当 dir=‘1’时,每来一个时钟信号,循环左移一位,当 dir=‘0’时, 每来一个时钟,循环右移一位。 另外,移位控制时钟可以选择为按键,即每按键一次相当于一个时钟信号,系统可以在 按键和系统分频时钟之间进行选择。

资源使用:

1)用 LED0~LED7 作为跑马灯输出显示,LED7 为高位,LED0 为低位;

2)SW0 为循环方向控制;

3)SW1 为工作允许 EN 控制端;

4)计数时钟频率为 1Hz,通过对 50Mhz 系统时钟分频得到;

5)扩展:可以由按键来控制循环(按键为 BTN_SOUTH),即每按一次 BTN_SOUTH, 则完成一次移位。通过 SW2 选择移位控制时钟沿。

源文件:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity run_led is
    Port(
        en,dir,sel,clk,con:in std_logic;
        y:out std_logic_vector(7 downto 0)
    );
end run_led;

architecture Behavioral of run_led is
signal input:std_logic;
signal clk_div:std_logic;
begin

process(clk)
variable clk_cnt:integer:=0;
variable clk_cnt_2:integer:=0;
begin 
    if(clk='1'and clk'event)then 
        clk_cnt_2:=clk_cnt_2+1;
        if(clk_cnt_2>=10000)then 
        clk_cnt:=clk_cnt+1;
        clk_cnt_2:=0;
        end if;
        if(clk_cnt<5000)then clk_div<='1';
        elsif(clk_cnt>=5000)then clk_div<='0';
        end if;
        if(clk_cnt>=10000)then clk_cnt:=0;
        end if; 
    end if;
end process;

process(clk,en,clk_div,con,sel)
    begin
        if(en='1')then
            if(sel='0')then input<=clk_div;
            elsif(sel='1')then input<=con;
            end if;
        elsif(en='0')then input<='0';
        end if;
end process;

process(input,dir)
variable count:integer:=0;
begin
if(input='1'and input'event)then 
    if(dir='1')then
        count:=count+1;
        if(count>7)then count:=0;end if;
    elsif(dir='0')then 
        count:=count-1;
        if(count<0)then count:=7;end if;
    end if;  
        
    if(count=0)then y<="00000001";
    elsif(count=1)then y<="00000010";
    elsif(count=2)then y<="00000100";
    elsif(count=3)then y<="00001000";
    elsif(count=4)then y<="00010000";
    elsif(count=5)then y<="00100000";
    elsif(count=6)then y<="01000000";
    elsif(count=7)then y<="10000000";
    else y<="11111111";
    end if;
    
end if;       
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity run_led_tb is
end run_led_tb;

architecture Behavioral of run_led_tb is
component run_led
    Port(
        en,dir,sel,clk,con:in std_logic;
        y:out std_logic_vector(7 downto 0)
    );
end component;

SIGNAL en,dir,sel,clk,con: std_logic;
SIGNAL y: std_logic_vector(7 downto 0);

begin
run_led_inst:run_led port map(en=>en,dir=>dir,sel=>sel,clk=>clk,con=>con,y=>y); 

clock:process
begin 
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

key:process
begin 
    con<='1';
    wait for 25ns;
    con<='0';
    wait for 25ns;
end process;

test:process
begin
    en<='0';
    sel<='1';
    dir<='1';
    wait for 25ns;
    en<='1';
    wait;

end process;


end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/18 13:02:24
#----------------------------------------------------------------------------------
set_property PACKAGE_PIN C9 [get_ports dir]
set_property PACKAGE_PIN AF12 [get_ports con]
set_property PACKAGE_PIN B9 [get_ports en]
set_property PACKAGE_PIN E10 [get_ports clk]
set_property PACKAGE_PIN G11 [get_ports sel]
set_property PACKAGE_PIN G16 [get_ports {y[0]}]
set_property PACKAGE_PIN H16 [get_ports {y[1]}]
set_property PACKAGE_PIN D16 [get_ports {y[2]}]
set_property PACKAGE_PIN D15 [get_ports {y[3]}]
set_property PACKAGE_PIN C18 [get_ports {y[4]}]
set_property PACKAGE_PIN C17 [get_ports {y[5]}]
set_property PACKAGE_PIN B19 [get_ports {y[6]}]
set_property PACKAGE_PIN C19 [get_ports {y[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {y[3]}]

set_property DRIVE 12 [get_ports {y[4]}]
set_property DRIVE 12 [get_ports {y[5]}]
set_property DRIVE 12 [get_ports {y[0]}]
set_property DRIVE 12 [get_ports {y[6]}]
set_property DRIVE 12 [get_ports {y[1]}]
set_property DRIVE 12 [get_ports {y[7]}]
set_property DRIVE 12 [get_ports {y[2]}]
set_property DRIVE 12 [get_ports {y[3]}]

set_property IOSTANDARD LVCMOS18 [get_ports dir]
set_property IOSTANDARD LVCMOS18 [get_ports con]
set_property IOSTANDARD LVCMOS18 [get_ports en]
set_property IOSTANDARD LVCMOS18 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports sel]


2.8 位并行全加器设计+数码管显示程序设计

注:数码管部分未使用优化代码

        其中 a_in,b_in:数据输入,使用板上开关(SW0~SW15); sum_out:运算结果输出,使用 LED 显示运算结果。

(1)用硬件描述语言实现 16 个七段数码管扫描显示模块

        七段数码管扫描显示模块电路如图所示,主要包括顶层的数码管扫描显示模块,以及输入数据向七段数码管进行译码的模块。

        该模块实现数码管扫描显示功能,扩展板上的 16 个数码管四个一组,分为 A,B,C,D 四组。模块管脚说明如下:clk 为系统的时钟输入,rst 信号为复位信号,data_in_A(15:0)为 A 组四个数码管的输入显示值,其中,data_in_A(3:0)对应于第一个数码管的输入显示值; data_in_A(7:4)对应第二个数码管的输入显示值;data_in_A(11:8)对应第三个数码管的输入显 示值;data_in_A(15:12)对应第四个数码管的输入显示值,其它各组与 A 组分配一致; data_in_B(15:0)为 B 组四个数码管的输入显示值;data_in_C(15:0)为 C 组四个数码管的输入显 示值;data_in_D(15:0)为 D 组四个数码管的输入显示值;seg_sel(3:0)为数码管选择编码输出 信号,seg_data(7:0)为数码管显示数据输出。 

        该模块实现将输入的 4 为二进制数转换为数码管显示的数据;其中,data_in(3:0)为输入 值,seg_data(7:0)为数码管编码的输出值。

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
    Port (
        clk,rst:in std_logic;
        a,b:in std_logic_vector(7 downto 0);
        c:in std_logic;
        
        c_out:out std_logic;
        sel_out:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
     );
end adder;

architecture Behavioral of adder is

component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        seg_sel:out std_logic_vector(3 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );
end component;
component decoder4_16
    Port (
        sel_in:in std_logic_vector(3 downto 0);
        sel_out:out std_logic_vector(15 downto 0)
     );
end component;

signal clk_out_line:std_logic;
signal sum_line:std_logic_vector(16 downto 0);
signal data_line:std_logic_vector(15 downto 0);
signal c_line:std_logic;
signal sel_out_line:std_logic_vector(3 downto 0);

begin

clk_div_inst:clk_div generic map(10000)port map(clk,clk_out_line);
seg_dis_inst:seg_dis port map(rst,clk_out_line,data_line,"0000000000000000","0000000000000000","0000000000000000",sel_out_line,seg_data);
decoder4_16_inst:decoder4_16 port map(sel_out_line,sel_out);

process(a,b,c)
begin  
    sum_line<=("00000000"&a)+("00000000"&b)+("0000000000000000"&c);
    data_line<=sum_line(15 downto 0);
    c_out<=sum_line(16);
end process;
    

end Behavioral;

模块:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder4_16 is
    Port (
        sel_in:in std_logic_vector(3 downto 0);
        sel_out:out std_logic_vector(15 downto 0)
     );
end decoder4_16;

architecture Behavioral of decoder4_16 is

begin

process(sel_in)
begin
    case sel_in is
    when "0000"=>sel_out<=not"0000000000000001";
    when "0001"=>sel_out<=not"0000000000000010";
    when "0010"=>sel_out<=not"0000000000000100";
    when "0011"=>sel_out<=not"0000000000001000";
    when "0100"=>sel_out<=not"0000000000010000";
    when "0101"=>sel_out<=not"0000000000100000";
    when "0110"=>sel_out<=not"0000000001000000";
    when "0111"=>sel_out<=not"0000000010000000";
    when "1000"=>sel_out<=not"0000000100000000";
    when "1001"=>sel_out<=not"0000001000000000";
    when "1010"=>sel_out<=not"0000010000000000";
    when "1011"=>sel_out<=not"0000100000000000";
    when "1100"=>sel_out<=not"0001000000000000";
    when "1101"=>sel_out<=not"0010000000000000";
    when "1110"=>sel_out<=not"0100000000000000";
    when "1111"=>sel_out<=not"1000000000000000";
    when others=>sel_out<=not"1111111111111111";
    end case;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seg_dis is
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        seg_sel:out std_logic_vector(3 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );

end seg_dis;

architecture Behavioral of seg_dis is
component data2seg
    port(
        data_in:in std_logic_vector(3 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );
end component;

signal data_in_line: std_logic_vector(3 downto 0);

type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal state,next_state:states;

begin   

data2seg_inst:data2seg port map(data_in_line,seg_data);

process(rst,clk)
begin 
    if(rst='1')then state<=s0;
    elsif(clk='1'and clk'event)then
        state<=next_state;
    end if;
end process;


process(state)
begin
    case state is
    when s0=>
        seg_sel<="0000";
        data_in_line<=data_in_A(3 downto 0);
        next_state<=s1;
    when s1=>
        seg_sel<="0001";
        data_in_line<=data_in_A(7 downto 4);
        next_state<=s2;
    when s2=>
        seg_sel<="0010";
        data_in_line<=data_in_A(11 downto 8);
        next_state<=s3;
    when s3=>
        seg_sel<="0011";
        data_in_line<=data_in_A(15 downto 12);
        next_state<=s4;
    
    when s4=>seg_sel<="0100";data_in_line<=data_in_B(3 downto 0);next_state<=s5;
    when s5=>seg_sel<="0101";data_in_line<=data_in_B(7 downto 4);next_state<=s6;
    when s6=>seg_sel<="0110";data_in_line<=data_in_B(11 downto 8);next_state<=s7;
    when s7=>seg_sel<="0111";data_in_line<=data_in_B(15 downto 12);next_state<=s8;
    
    when s8=>seg_sel<="1000";data_in_line<=data_in_C(3 downto 0);next_state<=s9;
    when s9=>seg_sel<="1001";data_in_line<=data_in_C(7 downto 4);next_state<=s10;
    when s10=>seg_sel<="1010";data_in_line<=data_in_C(11 downto 8);next_state<=s11;
    when s11=>seg_sel<="1011";data_in_line<=data_in_C(15 downto 12);next_state<=s12;
    
    when s12=>seg_sel<="1100";data_in_line<=data_in_D(3 downto 0);next_state<=s13;
    when s13=>seg_sel<="1101";data_in_line<=data_in_D(7 downto 4);next_state<=s14;
    when s14=>seg_sel<="1110";data_in_line<=data_in_D(11 downto 8);next_state<=s15;
    when s15=>seg_sel<="1111";data_in_line<=data_in_D(15 downto 12);next_state<=s0;
    
    when others=>state<=next_state;
    end case;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity data2seg is
    port(
        data_in:in std_logic_vector(3 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );

end data2seg;

architecture Behavioral of data2seg is
begin 
process(data_in)
begin
    case data_in is
        when "0000"=>seg_data<=not"00111111";
        when "0001"=>seg_data<=not"00000110";
        when "0010"=>seg_data<=not"01011011";
        when "0011"=>seg_data<=not"01001111";
        when "0100"=>seg_data<=not"01100110";
        when "0101"=>seg_data<=not"00110111";
        when "0110"=>seg_data<=not"01111101";
        when "0111"=>seg_data<=not"00000111";
        when "1000"=>seg_data<=not"01111111";
        when "1001"=>seg_data<=not"01101111";
        when "1010"=>seg_data<=not"01110111";
        when "1011"=>seg_data<=not"01111100";
        when "1100"=>seg_data<=not"00111000";
        when "1101"=>seg_data<=not"01011110";
        when "1110"=>seg_data<=not"01111001";
        when "1111"=>seg_data<=not"01110001";
        when others=>seg_data<=not"11111111";
    end case;
        
end process;
end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder_tb is
--  Port ( );
end adder_tb;

architecture Behavioral of adder_tb is
component adder
    Port (
        clk,rst:in std_logic;
        a,b:in std_logic_vector(7 downto 0);
        c:in std_logic;
        c_out:out std_logic;
        sel_out:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
     );
end component;
signal clk,rst :std_logic;
signal a,b     :std_logic_vector(7 downto 0);
signal c       :std_logic;
signal c_out   : std_logic;
signal sel_out : std_logic_vector(15 downto 0);
signal seg_data: std_logic_vector(7 downto 0);

begin
adder_inst:adder port map(clk,rst,a,b,c,c_out,sel_out,seg_data);

clock:process
begin
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

restart:process
begin
    rst<='1';
    wait for 25ns;
    rst<='0';
    wait;
end process;

test:process
begin
    a<="00100010";
    b<="01000100";
    c<='1';
    wait for 100ns;
    
    a<="11111111";
    b<="11111111";
    c<='1';
    wait;
end process;

end Behavioral;

xdc:

set_property PACKAGE_PIN E26 [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26 [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26 [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21 [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21 [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23 [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24 [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21 [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[0]}]

set_property PACKAGE_PIN E10 [get_ports clk]
set_property PACKAGE_PIN C9 [get_ports {a[0]}]
set_property PACKAGE_PIN B9 [get_ports {a[1]}]
set_property PACKAGE_PIN G11 [get_ports {a[2]}]
set_property PACKAGE_PIN F10 [get_ports {a[3]}]
set_property PACKAGE_PIN D10 [get_ports {a[4]}]
set_property PACKAGE_PIN E11 [get_ports {a[5]}]
set_property PACKAGE_PIN D11 [get_ports {a[6]}]
set_property PACKAGE_PIN A14 [get_ports {a[7]}]

set_property PACKAGE_PIN B10 [get_ports {b[0]}]
set_property PACKAGE_PIN A10 [get_ports {b[1]}]
set_property PACKAGE_PIN B15 [get_ports {b[2]}]
set_property PACKAGE_PIN A15 [get_ports {b[3]}]
set_property PACKAGE_PIN A13 [get_ports {b[4]}]
set_property PACKAGE_PIN A12 [get_ports {b[5]}]
set_property PACKAGE_PIN D8 [get_ports {b[6]}]
set_property PACKAGE_PIN D9 [get_ports {b[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b[7]}]

set_property IOSTANDARD LVCMOS18 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a[7]}]


set_property IOSTANDARD LVCMOS18 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports c_out]
set_property IOSTANDARD LVCMOS18 [get_ports c]

set_property PACKAGE_PIN J14 [get_ports c]
set_property PACKAGE_PIN G16 [get_ports c_out]
set_property PACKAGE_PIN J8 [get_ports rst]

#set_property IOSTANDARD LVCMOS18 [get_ports {sel_in[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {sel_in[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {sel_in[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {sel_in[3]}]

#set_property PACKAGE_PIN F8 [get_ports {sel_in[0]}]
#set_property PACKAGE_PIN F9 [get_ports {sel_in[1]}]
#set_property PACKAGE_PIN H11 [get_ports {sel_in[2]}]
#set_property PACKAGE_PIN H12 [get_ports {sel_in[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel_out[9]}]
set_property PACKAGE_PIN A23 [get_ports {sel_out[15]}]
set_property PACKAGE_PIN A24 [get_ports {sel_out[14]}]
set_property PACKAGE_PIN D26 [get_ports {sel_out[13]}]
set_property PACKAGE_PIN C26 [get_ports {sel_out[12]}]
set_property PACKAGE_PIN A20 [get_ports {sel_out[11]}]
set_property PACKAGE_PIN J25 [get_ports {sel_out[10]}]
set_property PACKAGE_PIN J24 [get_ports {sel_out[9]}]
set_property PACKAGE_PIN H22 [get_ports {sel_out[8]}]
set_property PACKAGE_PIN K21 [get_ports {sel_out[7]}]
set_property PACKAGE_PIN L23 [get_ports {sel_out[6]}]
set_property PACKAGE_PIN B25 [get_ports {sel_out[5]}]
set_property PACKAGE_PIN B26 [get_ports {sel_out[4]}]
set_property PACKAGE_PIN C24 [get_ports {sel_out[3]}]
set_property PACKAGE_PIN D21 [get_ports {sel_out[2]}]
set_property PACKAGE_PIN C22 [get_ports {sel_out[1]}]
set_property PACKAGE_PIN B20 [get_ports {sel_out[0]}]

3.阵列乘法器设计

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier_seg is
    Port (
        rst,clk:in std_logic;
        a_in,b_in:in std_logic_vector(7 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );
end array_multiplier_seg;

architecture Behavioral of array_multiplier_seg is

component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component array_multiplier
    Port (
        clk:in std_logic;
        a_in,b_in:in std_logic_vector(7 downto 0);
        sum_out:out std_logic_vector(15 downto 0)
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        seg_sel:out std_logic_vector(3 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );
end component;
component decoder4_16
    Port (
        sel_in:in std_logic_vector(3 downto 0);
        sel_out:out std_logic_vector(15 downto 0)
     );
end component;

signal clk_out_line:std_logic;
signal sum_out_line:std_logic_vector(15 downto 0);
signal seg_dig_line:std_logic_vector(3 downto 0);

begin

clk_div_inst:clk_div generic map(10000)port map(clk,clk_out_line);
array_multiplier_inst:array_multiplier port map(clk_out_line,a_in,b_in,sum_out_line);
seg_dis_inst:seg_dis port map(rst,clk_out_line,sum_out_line,"0000000000000000","0000000000000000","0000000000000000",seg_dig_line,seg_data);
decoder4_16_inst:decoder4_16 port map(seg_dig_line,seg_dig);

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier is
    Port (
        clk:in std_logic;
        a_in,b_in:in std_logic_vector(7 downto 0);
        sum_out:out std_logic_vector(15 downto 0)
    );
end array_multiplier;

architecture Behavioral of array_multiplier is
component array_multiplier_top
    Port (
        a_in:in std_logic;
        b_in:in std_logic_vector(7 downto 0);
        s:out std_logic_vector(7 downto 0)
     );
end component;
component array_multiplier_unit
    Port (
        x_in:in std_logic;
        y_in:in std_logic_vector(7 downto 0);
        c_in:in std_logic_vector(6 downto 0);
        z_in:in std_logic_vector(7 downto 0);
        c_out:out std_logic_vector(6 downto 0);
        z_out:out std_logic_vector(7 downto 0)
     );
end component;
component array_multiplier_low
    Port (
        z_in,c_in:in std_logic_vector(6 downto 0);
        s_out:out std_logic_vector(7 downto 0)
     );
end component;

signal z_in0:std_logic_vector(7 downto 0);
signal z_in1:std_logic_vector(7 downto 0);
signal z_in2:std_logic_vector(7 downto 0);
signal z_in3:std_logic_vector(7 downto 0);
signal z_in4:std_logic_vector(7 downto 0);
signal z_in5:std_logic_vector(7 downto 0);
signal z_in6:std_logic_vector(7 downto 0);
signal z_in7:std_logic_vector(7 downto 0);
signal c_in1:std_logic_vector(6 downto 0);
signal c_in2:std_logic_vector(6 downto 0);
signal c_in3:std_logic_vector(6 downto 0);
signal c_in4:std_logic_vector(6 downto 0);
signal c_in5:std_logic_vector(6 downto 0);
signal c_in6:std_logic_vector(6 downto 0);
signal c_in7:std_logic_vector(6 downto 0);

begin

array_multiplier_top_inst:array_multiplier_top port map(a_in(0),b_in,z_in0);
array_multiplier_unit_inst1:array_multiplier_unit port map(a_in(1),b_in,"0000000",z_in0,c_in1,z_in1);
array_multiplier_unit_inst2:array_multiplier_unit port map(a_in(2),b_in,c_in1,z_in1,c_in2,z_in2);
array_multiplier_unit_inst3:array_multiplier_unit port map(a_in(3),b_in,c_in2,z_in2,c_in3,z_in3);
array_multiplier_unit_inst4:array_multiplier_unit port map(a_in(4),b_in,c_in3,z_in3,c_in4,z_in4);
array_multiplier_unit_inst5:array_multiplier_unit port map(a_in(5),b_in,c_in4,z_in4,c_in5,z_in5);
array_multiplier_unit_inst6:array_multiplier_unit port map(a_in(6),b_in,c_in5,z_in5,c_in6,z_in6);
array_multiplier_unit_inst7:array_multiplier_unit port map(a_in(7),b_in,c_in6,z_in6,c_in7,z_in7);
array_multiplier_low_inst:array_multiplier_low port map(z_in7(7 downto 1),c_in7,sum_out(15 downto 8));

process(clk,a_in,b_in)
begin
    sum_out(0)<=z_in0(0);
    sum_out(1)<=z_in1(0);
    sum_out(2)<=z_in2(0);
    sum_out(3)<=z_in3(0);
    sum_out(4)<=z_in4(0);
    sum_out(5)<=z_in5(0);
    sum_out(6)<=z_in6(0);
    sum_out(7)<=z_in7(0);
end process;

end Behavioral;

模块:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier_top is
    Port (
        a_in:in std_logic;
        b_in:in std_logic_vector(7 downto 0);
        s:out std_logic_vector(7 downto 0)
     );
end array_multiplier_top;

architecture Behavioral of array_multiplier_top is

begin

process(a_in,b_in)
begin
    for i in 0 to 7 loop
       s(i)<=a_in and b_in(i); 
    end loop;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier_unit is
    Port (
        x_in:in std_logic;
        y_in:in std_logic_vector(7 downto 0);
        c_in:in std_logic_vector(6 downto 0);
        z_in:in std_logic_vector(7 downto 0);
        c_out:out std_logic_vector(6 downto 0);
        z_out:out std_logic_vector(7 downto 0)
     );
end array_multiplier_unit;

architecture Behavioral of array_multiplier_unit is
component adder_1bit
    Port (
        a,b,c_in:in std_logic;
        s,c_out:out std_logic
     );
end component;

signal a_line:std_logic_vector(7 downto 0);

begin

adder_1bit_inst1:adder_1bit port map(a_line(0),c_in(0),z_in(1),z_out(0),c_out(0));
adder_1bit_inst2:adder_1bit port map(a_line(1),c_in(1),z_in(2),z_out(1),c_out(1));
adder_1bit_inst3:adder_1bit port map(a_line(2),c_in(2),z_in(3),z_out(2),c_out(2));
adder_1bit_inst4:adder_1bit port map(a_line(3),c_in(3),z_in(4),z_out(3),c_out(3));
adder_1bit_inst5:adder_1bit port map(a_line(4),c_in(4),z_in(5),z_out(4),c_out(4));
adder_1bit_inst6:adder_1bit port map(a_line(5),c_in(5),z_in(6),z_out(5),c_out(5));
adder_1bit_inst7:adder_1bit port map(a_line(6),c_in(6),z_in(7),z_out(6),c_out(6));

process(x_in,y_in)
begin 
    z_out(7)<=x_in and y_in(7);
    for i in 0 to 7 loop
       a_line(i)<=x_in and y_in(i);
    end loop;
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier_low is
    Port (
        z_in,c_in:in std_logic_vector(6 downto 0);
        s_out:out std_logic_vector(7 downto 0)
     );
end array_multiplier_low;

architecture Behavioral of array_multiplier_low is
component adder_1bit
    Port (
        a,b,c_in:in std_logic;
        s,c_out:out std_logic
     );
end component;

signal c_line:std_logic_vector(5 downto 0);

begin

adder_1bit_inst0:adder_1bit port map(z_in(0),c_in(0),'0',s_out(0),c_line(0));
adder_1bit_inst1:adder_1bit port map(z_in(1),c_in(1),c_line(0),s_out(1),c_line(1));
adder_1bit_inst2:adder_1bit port map(z_in(2),c_in(2),c_line(1),s_out(2),c_line(2));
adder_1bit_inst3:adder_1bit port map(z_in(3),c_in(3),c_line(2),s_out(3),c_line(3));
adder_1bit_inst4:adder_1bit port map(z_in(4),c_in(4),c_line(3),s_out(4),c_line(4));
adder_1bit_inst5:adder_1bit port map(z_in(5),c_in(5),c_line(4),s_out(5),c_line(5));
adder_1bit_inst6:adder_1bit port map(z_in(6),c_in(6),c_line(5),s_out(6),s_out(7));

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder_1bit is
    Port (
        a,b,c_in:in std_logic;
        s,c_out:out std_logic
     );
end adder_1bit;

architecture Behavioral of adder_1bit is

begin

process(a,b,c_in)
begin
    s<=a xor b xor c_in;
    c_out<=(a and b)or((a xor b)and c_in);
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_multiplier_tb is
--  Port ( );
end array_multiplier_tb;

architecture Behavioral of array_multiplier_tb is
component array_multiplier_seg
    Port (
        rst,clk:in std_logic;
        a_in,b_in:in std_logic_vector(7 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)
    );
end component;

signal rst,clk:std_logic;
signal a_in,b_in:std_logic_vector(7 downto 0);
signal seg_dig:std_logic_vector(15 downto 0);
signal seg_data:std_logic_vector(7 downto 0);


begin

array_multiplier_seg_inst:array_multiplier_seg port map(rst,clk,a_in,b_in,seg_dig,seg_data);

clock:process
begin 
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

restart:process
begin
    rst<='1';
    wait for 25ns;
    rst<='0';
    wait;
end process;

test:process
begin
    a_in<="10111101";
    b_in<="11001010";
    wait;
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/18 13:02:24
#----------------------------------------------------------------------------------
#CLK_100M
set_property PACKAGE_PIN E10 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports clk]

#SW0~15
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {a_in[7]}]
set_property PACKAGE_PIN C9 [get_ports {a_in[0]}]
set_property PACKAGE_PIN B9 [get_ports {a_in[1]}]
set_property PACKAGE_PIN G11 [get_ports {a_in[2]}]
set_property PACKAGE_PIN F10 [get_ports {a_in[3]}]
set_property PACKAGE_PIN D10 [get_ports {a_in[4]}]
set_property PACKAGE_PIN E11 [get_ports {a_in[5]}]
set_property PACKAGE_PIN D11 [get_ports {a_in[6]}]
set_property PACKAGE_PIN A14 [get_ports {a_in[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {b_in[7]}]
set_property PACKAGE_PIN B10 [get_ports {b_in[0]}]
set_property PACKAGE_PIN A10 [get_ports {b_in[1]}]
set_property PACKAGE_PIN B15 [get_ports {b_in[2]}]
set_property PACKAGE_PIN A15 [get_ports {b_in[3]}]
set_property PACKAGE_PIN A13 [get_ports {b_in[4]}]
set_property PACKAGE_PIN A12 [get_ports {b_in[5]}]
set_property PACKAGE_PIN D8 [get_ports {b_in[6]}]
set_property PACKAGE_PIN D9 [get_ports {b_in[7]}]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23 [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24 [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26 [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26 [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20 [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25 [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24 [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22 [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21 [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23 [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25 [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26 [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24 [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21 [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22 [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20 [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26 [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26 [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26 [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21 [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21 [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23 [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24 [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21 [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_data[0]}]


set_property PACKAGE_PIN J8 [get_ports rst]
set_property IOSTANDARD LVCMOS18 [get_ports rst]

4.先进先出 FIFO 的设计

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
-- Module Name: FIFO_ring_test - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FIFO_ring_test is
generic(
    CLK_FRE:integer:=100000000;
    cycle_max:positive:=3;--最大读写圈数
    depth:positive:=3;
    width:positive:=8
);
    Port(
        clk:in std_logic;
        rst:in std_logic;
        key_in:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        wr:in std_logic;
        rd:in std_logic;
        
        empty:out std_logic;
        full:out std_logic;
        data_out:out std_logic_vector(7 downto 0)
    );
end FIFO_ring_test;

architecture Behavioral of FIFO_ring_test is

component key_stroke
    generic(CLK_FRE:integer:=100000000);
    Port (
        clk:in std_logic;
        reset:in std_logic;
        key_in:in std_logic;
        output:out std_logic           
    );
end component;
component FIFO_ring
generic(
    cycle_max:positive:=3;--最大读写圈数
    depth:positive:=3;
    width:positive:=8
);
    Port(
        clk,clk_rd,clk_wr:in std_logic;
        rst:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        wr:in std_logic;
        rd:in std_logic;
        
        empty:out std_logic;
        full:out std_logic;
        data_out:out std_logic_vector(7 downto 0)
    );
end component;

signal out_put:std_logic;

begin
key_stroke_inst:key_stroke generic map(CLK_FRE)port map(clk=>clk,reset=>rst,key_in=>key_in,output=>out_put);
FIFO_ring_inst:FIFO_ring generic map(cycle_max,depth,width)port map(rst=>rst,clk=>clk,clk_rd=>out_put,clk_wr=>out_put,wr=>wr,rd=>rd,data_in=>data_in,full=>full,empty=>empty,data_out=>data_out);

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
-- Module Name: FIFO_ring - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FIFO_ring is
generic(
    cycle_max:positive:=3;--最大读写圈数
    depth:positive:=3;
    width:positive:=8
);
    Port(
        clk,clk_rd,clk_wr:in std_logic;
        rst:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        wr:in std_logic;
        rd:in std_logic;
        
        empty:out std_logic;
        full:out std_logic;
        data_out:out std_logic_vector(7 downto 0)
    );
end FIFO_ring;

architecture Behavioral of FIFO_ring is
component duaram
generic(
    depth:positive:=3;
    width:positive:=8
);
Port(
    clka:in std_logic;
    wr:in std_logic;
    wr_en:in std_logic;
    addra:in std_logic_vector(depth-1 downto 0);
    datain:in std_logic_vector(width-1 downto 0);
    
    clkb:in std_logic;
    rd:in std_logic;
    rd_en:in std_logic;
    addrb:in std_logic_vector(depth-1 downto 0);
    dataout:out std_logic_vector(width-1 downto 0)
); 
end component;
component FIFO_ring_duaram_controller
generic(
    cycle_max:positive;--最大读写圈数
    depth:positive
);
Port(
    rst:in std_logic;
    clk,clka,clkb:in std_logic;
    wq:in std_logic;
    rq:in std_logic;
    full:out std_logic;
    empty:out std_logic;
    
    wr_pt:out std_logic_vector(depth-1 downto 0);
    rd_pt:out std_logic_vector(depth-1 downto 0)
);
end component;

signal rp_line:std_logic_vector(depth-1 downto 0);
signal wp_line:std_logic_vector(depth-1 downto 0);
signal empty_line:std_logic;
signal full_line:std_logic;

begin
duaram_inst:duaram generic map(depth,width)port map(clka=>clk_wr,clkb=>clk_rd,datain=>data_in,dataout=>data_out,addra=>wp_line,addrb=>rp_line,rd=>rd,wr=>wr,rd_en=>empty_line,wr_en=>full_line);
FIFO_ring_duaram_controller_inst:FIFO_ring_duaram_controller generic map(cycle_max,depth)port map(rst=>rst,clk=>clk,clkb=>clk_rd,clka=>clk_wr,wq=>wr,rq=>rd,full=>full_line,empty=>empty_line,wr_pt=>wp_line,rd_pt=>rp_line);

process(empty_line,full_line)
begin
    empty<=empty_line;
    full<=full_line;
end process;

end Behavioral;

模块:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
-- Module Name: FIFO_ring - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity duaram is
    generic(
        depth:positive;
        width:positive
    );
    Port(
        clka:in std_logic;
        wr:in std_logic;
        wr_en:in std_logic;
        addra:in std_logic_vector(depth-1 downto 0);
        datain:in std_logic_vector(width-1 downto 0);
        
        clkb:in std_logic;
        rd:in std_logic;
        rd_en:in std_logic;
        addrb:in std_logic_vector(depth-1 downto 0);
        dataout:out std_logic_vector(width-1 downto 0)
    );
end duaram;

architecture Behavioral of duaram is
type ram is array(2**depth-1 downto 0)of std_logic_vector(width-1 downto 0);
signal dualram:ram;
begin

    process(clka)
    begin
        if(clka'event and clka='1')then
            if(wr='0'and wr_en='0')then dualram(conv_integer(addra))<=datain;end if;
        end if;
    end process;
    
    process(clkb)
    begin
        if(clkb'event and clkb='1')then
            if(rd='0'and rd_en='0')then dataout<=dualram(conv_integer(addrb));end if;
        end if;
    end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
-- Module Name: FIFO_ring_duaram_controller - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FIFO_ring_duaram_controller is
generic(
    cycle_max:positive;--最大读写圈数
    depth:positive
);
Port(
    rst:in std_logic;
    clk,clka,clkb:in std_logic;
    wq:in std_logic;
    rq:in std_logic;
    full:out std_logic;
    empty:out std_logic;
    
    wr_pt:out std_logic_vector(depth-1 downto 0);
    rd_pt:out std_logic_vector(depth-1 downto 0)
);
end FIFO_ring_duaram_controller;

architecture Behavioral of FIFO_ring_duaram_controller is
signal wr_pt_t:std_logic_vector(depth+cycle_max-1 downto 0);
signal rd_pt_t:std_logic_vector(depth+cycle_max-1 downto 0);
signal full_line:std_logic;
signal empty_line:std_logic;
begin

--write_pointer
process(rst,clka)
begin
    if(rst='0')then
        wr_pt_t<=(others=>'0');
    elsif(clka'event and clka='1')then
        if (wq='0'and full_line='0')then wr_pt_t<=wr_pt_t+1;end if;
    end if;     
end process;

--read_pointer
process(rst,clkb)
begin
    if(rst='0')then
        rd_pt_t<=(others=>'0');
    elsif(clkb'event and clkb='1')then
        if (rq='0'and empty_line='0')then 
rd_pt_t<=rd_pt_t+1;
end if;
    end if;
end process;

--judge_status
process(rst,clk)
begin
    if(rst='0')then empty_line<='1';full_line<='0';
    elsif(clk'event and clk='1')then
        if(wr_pt_t=rd_pt_t)then empty_line<='1';full_line<='0';
        elsif(wr_pt_t=rd_pt_t+2**depth)then empty_line<='0';full_line<='1';
        else empty_line<='0';full_line<='0';
        end if;
    end if;  
end process;

process(wr_pt_t)
begin wr_pt<=wr_pt_t(depth-1 downto 0);
end process;

process(rd_pt_t)
begin rd_pt<=rd_pt_t(depth-1 downto 0);
end process;

process(empty_line)
begin empty<=empty_line;
end process;

process(full_line)
begin full<=full_line;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
-- Module Name: FIFO_ring_tb - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FIFO_ring_tb is
--  Port ( );
end FIFO_ring_tb;

architecture Behavioral of FIFO_ring_tb is

component FIFO_ring_test
generic(
    CLK_FRE:integer:=100000000;
    cycle_max:positive:=3;--最大读写圈数
    depth:positive:=3;
    width:positive:=8
);
    Port(
        clk:in std_logic;
        rst:in std_logic;
        key_in:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        wr:in std_logic;
        rd:in std_logic;
        
        empty:out std_logic;
        full:out std_logic;
        data_out:out std_logic_vector(7 downto 0)
    );
end component;

signal clk:std_logic;
signal rst:std_logic;
signal key_in:std_logic;
signal data_in:std_logic_vector(7 downto 0);
signal wr:std_logic;
signal rd:std_logic;
signal empty:std_logic;
signal full:std_logic;
signal data_out:std_logic_vector(7 downto 0);

begin

FIFO_ring_test_inst:FIFO_ring_test generic map(100000000,3,8)port map(clk,rst,key_in,data_in,wr,rd,empty,full,data_out);

clock:process
begin
    clk<='0';
    wait for 5ns;
    clk<='1';
    wait for 5ns;
end process;

reset:process
begin
    rst<='0';
    wait for 25ns;
    rst<='1';
    wait;
end process;

test:process
begin
    rd<='1';
    wr<='1';
    data_in<="00000000";
    key_in<='0';
    wait for 4ms;
    
    rd<='1';
    wr<='0';
    data_in<="00000001";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00000010";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00000100";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00001000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00010000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00100000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="01000000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="10000000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="11111111";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="00001111";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<="11110000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    
    wr<='1';
    rd<='0';
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    
    rd<='1';
    wr<='0';
    data_in<=not"00000001";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00000010";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00000100";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00001000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00010000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00100000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"01000000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"10000000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"11111111";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"00001111";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    data_in<=not"11110000";
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    
    wr<='1';
    rd<='0';
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    wait for 4ms;
    key_in<='1';
    wait for 4ms;
    key_in<='0';
    wait for 4ms;
    
    wait;

end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/18 13:02:24
#----------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {data_in[7]}]
set_property PACKAGE_PIN C9 [get_ports {data_in[0]}]
set_property PACKAGE_PIN B9 [get_ports {data_in[1]}]
set_property PACKAGE_PIN G11 [get_ports {data_in[2]}]
set_property PACKAGE_PIN F10 [get_ports {data_in[3]}]
set_property PACKAGE_PIN D10 [get_ports {data_in[4]}]
set_property PACKAGE_PIN E11 [get_ports {data_in[5]}]
set_property PACKAGE_PIN D11 [get_ports {data_in[6]}]
set_property PACKAGE_PIN A14 [get_ports {data_in[7]}]

set_property PACKAGE_PIN E10 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports clk]

#sw31
set_property PACKAGE_PIN J8 [get_ports rst]
set_property IOSTANDARD LVCMOS18 [get_ports rst]
#sw30
set_property PACKAGE_PIN J14 [get_ports key_in]
set_property IOSTANDARD LVCMOS18 [get_ports key_in]
#sw29
set_property PACKAGE_PIN H9 [get_ports wr]
set_property IOSTANDARD LVCMOS18 [get_ports wr]
#sw28
set_property PACKAGE_PIN H8 [get_ports rd]
set_property IOSTANDARD LVCMOS18 [get_ports rd]
#led15
set_property PACKAGE_PIN L20 [get_ports empty]
set_property IOSTANDARD LVCMOS33 [get_ports empty]
#led11
set_property PACKAGE_PIN J20 [get_ports full]
set_property IOSTANDARD LVCMOS33 [get_ports full]
#led0-7
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[6]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[7]}]
set_property PACKAGE_PIN G16			[get_ports {data_out[0]}]
set_property PACKAGE_PIN H16 			[get_ports {data_out[1]}]
set_property PACKAGE_PIN D16 			[get_ports {data_out[2]}]
set_property PACKAGE_PIN D15 			[get_ports {data_out[3]}]
set_property PACKAGE_PIN C18 			[get_ports {data_out[4]}]
set_property PACKAGE_PIN C17 			[get_ports {data_out[5]}]
set_property PACKAGE_PIN B19 			[get_ports {data_out[6]}]
set_property PACKAGE_PIN C19 			[get_ports {data_out[7]}]

5.PC 程序计数器设计

 PC 功能分析 加 1 功能、更新地址功能、PC 数值送到数据总线

 PC 功能实现

1)全局异步复位功能

         ADDR<=“000000000000”;

         数据总线高阻态;

2)加 1 功能

         clk_PC 上升沿有效;

         M_PC 高电平有效,PC+1=>ADDR;

3)地址更新功能

         clk_PC 上升沿有效,nLD_PC 低电平有效,新的 PC=>ADDR;

         PC 数值送到数据总线,nPCH 和 nPCL 低电平有效,注意分两次输出到总线上,先高 8 位后低 8 位。

注:自行添加按键消抖模块

源码:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pc is
    Port (        
        rst,clk_PC,M_PC,nLD_PC:in std_logic;
        PC_in:in std_logic_vector(11 downto 0);
        
        DATA_BUS:inout std_logic_vector(7 downto 0);
        
        nPCH,nPCL:out std_logic
     );
end pc;

architecture Behavioral of pc is

signal pc_count:std_logic_vector(11 downto 0);
signal ADDR:std_logic_vector(11 downto 0);


begin

process(rst,clk_PC)
variable addr_count:integer:=0;
begin
    if(rst='1')then 
        pc_count<=PC_in;
        ADDR<=pc_count;
        DATA_BUS<="XXXXXXXX";
        nPCH<='1';nPCL<='1';

    elsif(clk_PC='1'and clk_PC'event)then
        if(addr_count=0)then pc_count<=pc_count+1;end if;
        if(M_PC='1')then ADDR<=pc_count;end if;
        if(nLD_PC='0')then 
            if(addr_count=0)then DATA_BUS<="0000"& ADDR(11 downto 8);addr_count:=addr_count+1;nPCH<='0';nPCL<='1';
            elsif(addr_count=1)then DATA_BUS<=ADDR(7 downto 0);addr_count:=addr_count-1;nPCH<='1';nPCL<='0';
            end if;
        end if;
    end if;
end process;



end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/18 13:02:24
#----------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {PC_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {PC_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {PC_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {PC_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {PC_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {PC_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {PC_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {PC_in[7]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[8]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[9]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[10]}]
set_property IOSTANDARD LVCMOS18    [get_ports {PC_in[11]}]
set_property PACKAGE_PIN B10        [get_ports {PC_in[8]}]
set_property PACKAGE_PIN A10        [get_ports {PC_in[9]}]
set_property PACKAGE_PIN B15        [get_ports {PC_in[10]}]
set_property PACKAGE_PIN A15        [get_ports {PC_in[11]}]


set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[6]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {DATA_BUS[7]}]
set_property PACKAGE_PIN G16			[get_ports {DATA_BUS[0]}]
set_property PACKAGE_PIN H16 			[get_ports {DATA_BUS[1]}]
set_property PACKAGE_PIN D16 			[get_ports {DATA_BUS[2]}]
set_property PACKAGE_PIN D15 			[get_ports {DATA_BUS[3]}]
set_property PACKAGE_PIN C18 			[get_ports {DATA_BUS[4]}]
set_property PACKAGE_PIN C17 			[get_ports {DATA_BUS[5]}]
set_property PACKAGE_PIN B19 			[get_ports {DATA_BUS[6]}]
set_property PACKAGE_PIN C19 			[get_ports {DATA_BUS[7]}]

#sw31
set_property PACKAGE_PIN J8 [get_ports rst]
set_property IOSTANDARD LVCMOS18 [get_ports rst]
#sw30
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_PC]
set_property PACKAGE_PIN J14 [get_ports clk_PC]
set_property IOSTANDARD LVCMOS18 [get_ports clk_PC]
#sw29
set_property PACKAGE_PIN H9 [get_ports M_PC]
set_property IOSTANDARD LVCMOS18 [get_ports M_PC]
#sw28
set_property PACKAGE_PIN H8 [get_ports nLD_PC]
set_property IOSTANDARD LVCMOS18 [get_ports nLD_PC]

#led15
set_property PACKAGE_PIN L20 [get_ports nPCH]
set_property IOSTANDARD LVCMOS33 [get_ports nPCH]
#led11
set_property PACKAGE_PIN J20 [get_ports nPCL]
set_property IOSTANDARD LVCMOS33 [get_ports nPCL]

6.程序存储器 ROM 设计

源码:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_textio.ALL;
use std.textio.all;

entity ROM is
    generic(
        depth:positive:=12;
        width:positive:=8
    );
    Port (
        clk_ROM,M_ROM,ROM_EN:in std_logic;
        addr:in std_logic_vector(11 downto 0);
        DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end ROM;

architecture Behavioral of ROM is
type matrix is array (integer range<>)of std_logic_vector(width-1 downto 0);
signal rom:matrix(0 to 2**depth-1);

procedure load_rom (signal data_word:out matrix)is
file romfile:text open read_mode is "romfile.dat";
variable lbuf:line;
variable i:integer:=0;
variable fdata:std_logic_vector(7 downto 0);
begin
    while(not endfile(romfile)and i<2**depth)loop
        readline(romfile,lbuf);
        read(lbuf,fdata);
        data_word(i)<=fdata;
        i:=i+1;
    end loop;
end procedure;

begin

load_rom(rom);

process(clk_ROM)
begin
    if(clk_ROM='1'and clk_ROM'event)then        
        if(ROM_EN='0'and M_ROM='1')then
            DATA_BUS<=rom(conv_integer(addr));
        else DATA_BUS<=(others=>'Z');
        end if;
    end if;
end process;        
        
end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 13:02:24
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM_tb is
--  Port ( );
end ROM_tb;

architecture Behavioral of ROM_tb is
component ROM
    generic(
        depth:positive:=12;
        width:positive:=8
    );
    Port (
        clk_ROM,M_ROM,ROM_EN:in std_logic;
        addr:in std_logic_vector(11 downto 0);
        DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end component;

signal rst:std_logic;
signal clk_ROM,M_ROM,ROM_EN:std_logic;
signal addr:std_logic_vector(11 downto 0);
signal DATA_BUS:std_logic_vector(7 downto 0);

begin

ROM_inst:ROM generic map(12,8)port map(clk_ROM,M_ROM,ROM_EN,addr,DATA_BUS);

clock:process
begin
    clk_ROM<='1';
    wait for 5ns;
    clk_ROM<='0';
    wait for 5ns;
end process;

test:process
begin
    M_ROM<='0';
    ROM_EN<='1';
    addr<=(others=>'0');
    wait for 25ns;
    M_ROM<='1';
    wait for 25ns;
    ROM_EN<='0';
    
    wait for 5ns;
    addr<="000000000000";
    wait for 20ns;  
    wait for 5ns;
    addr<="000000000001";
    wait for 20ns;
    wait for 5ns;
    addr<="000000000010";
    wait for 20ns;
    wait for 5ns;
    addr<="000000000011";
    wait for 20ns;
    
    wait;

end process;

end Behavioral;

xdc:

set_property IOSTANDARD LVCMOS18 [get_ports {addr[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[7]}]
set_property PACKAGE_PIN C9 [get_ports {addr[0]}]
set_property PACKAGE_PIN B9 [get_ports {addr[1]}]
set_property PACKAGE_PIN G11 [get_ports {addr[2]}]
set_property PACKAGE_PIN F10 [get_ports {addr[3]}]
set_property PACKAGE_PIN D10 [get_ports {addr[4]}]
set_property PACKAGE_PIN E11 [get_ports {addr[5]}]
set_property PACKAGE_PIN D11 [get_ports {addr[6]}]
set_property PACKAGE_PIN A14 [get_ports {addr[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {addr[11]}]
set_property PACKAGE_PIN B10 [get_ports {addr[8]}]
set_property PACKAGE_PIN A10 [get_ports {addr[9]}]
set_property PACKAGE_PIN B15 [get_ports {addr[10]}]
set_property PACKAGE_PIN A15 [get_ports {addr[11]}]

set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[7]}]
set_property PACKAGE_PIN G16 [get_ports {DATA_BUS[0]}]
set_property PACKAGE_PIN H16 [get_ports {DATA_BUS[1]}]
set_property PACKAGE_PIN D16 [get_ports {DATA_BUS[2]}]
set_property PACKAGE_PIN D15 [get_ports {DATA_BUS[3]}]
set_property PACKAGE_PIN C18 [get_ports {DATA_BUS[4]}]
set_property PACKAGE_PIN C17 [get_ports {DATA_BUS[5]}]
set_property PACKAGE_PIN B19 [get_ports {DATA_BUS[6]}]
set_property PACKAGE_PIN C19 [get_ports {DATA_BUS[7]}]

#sw30
set_property PACKAGE_PIN J14 [get_ports ROM_EN]
set_property IOSTANDARD LVCMOS18 [get_ports ROM_EN]

#sw31
set_property PACKAGE_PIN J8 [get_ports M_ROM]
set_property IOSTANDARD LVCMOS18 [get_ports M_ROM]

set_property PACKAGE_PIN E10 [get_ports clk_ROM]
set_property IOSTANDARD LVCMOS18 [get_ports clk_ROM]

7.加减交替除法器

原码加减交替除法器的运算法则:

1)除法运算前,应满足条件:X*<Y*,且 Y*≠0,否则,按溢出或非法除数处理;

2)符号位不参与运算,单独处理:qf= xf xor yf ;

3)部分余数采用单符号位或双符号位;

4)每步部分余数运算规则:

        ①若余数 R≥0, 则商上 1,左移一次,减除数;

        ②若余数 R<0, 则商上 0,左移一次,加除数。

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity divider_origin_test is
    Port(
        rst,clk,start:in std_logic;
        ain:in std_logic_vector(15 downto 0);--除数(要求除数大于被除数!)
        bin:in std_logic_vector(7 downto 0);--被除数
        done:out std_logic;

        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end divider_origin_test;

architecture Behavioral of divider_origin_test is
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        sel_out:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;
component divider_origin
    Port(
        clk,start:in std_logic;
        ain:in std_logic_vector(15 downto 0);--除数(要求除数大于被除数!)
        bin:in std_logic_vector(7 downto 0);--被除数
        done:out std_logic;

        s,r:out std_logic_vector(7 downto 0)
    );
end component;

signal clk_line:std_logic;
signal s,r:std_logic_vector(7 downto 0);
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0);

begin

clk_div_inst:clk_div generic map(10000)port map(rst,clk,clk_line);
seg_dis_inst:seg_dis port map(rst,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);
divider_origin_inst:divider_origin port map(clk,start,ain,bin,done,s,r);

process(s,r,ain,bin)
begin
    data_in_A<="00000000"&s;
    data_in_B<="00000000"&r;
    data_in_C<="00000000"&bin;
    data_in_D<=ain;
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divider_origin is
    Port(
        clk,start:in std_logic;
        ain:in std_logic_vector(15 downto 0);--除数(要求除数大于被除数!)
        bin:in std_logic_vector(7 downto 0);--被除数
        done:out std_logic;

        s,r:out std_logic_vector(7 downto 0)
    );
end divider_origin;

architecture Behavioral of divider_origin is

component divider_origin_ctrl
    Port (
        clk,start:in std_logic;
        clkout,rstall,done:out std_logic
     );
end component;
component divider_origin_16bitreg
    Port (
        clk,rst:in std_logic;
        ain:in std_logic_vector(15 downto 0);
        d:in std_logic_vector(8 downto 0);
        c_out:out std_logic;
        q:out std_logic_vector(15 downto 0)
     );
end component;
component divider_origin_selector
    Port (
        clk,rst:in std_logic;
        a0:in std_logic;
        din:in std_logic_vector(7 downto 0);
        cout:out std_logic;
        dout:out std_logic_vector(7 downto 0)
     );
end component;
component divider_origin_8bitadder
    Port (
        clk,rst:in std_logic;
        cina,cinb:in std_logic;
        ain,bin:in std_logic_vector(7 downto 0);
        sout:out std_logic_vector(8 downto 0)
     );
end component;

signal clk_line:std_logic;
signal rst_line:std_logic;
signal cina_line,cinb_line:std_logic;
signal bin_line:std_logic_vector(7 downto 0);
signal sout_line:std_logic_vector(8 downto 0);
signal q_line:std_logic_vector(15 downto 0);

begin
divider_origin_ctrl_inst:divider_origin_ctrl port map(clk=>clk,start=>start,clkout=>clk_line,rstall=>rst_line,done=>done);
divider_origin_16bitreg_inst:divider_origin_16bitreg port map(clk=>clk_line,rst=>rst_line,ain=>ain,d=>sout_line,c_out=>cina_line,q=>q_line);
divider_origin_selector_inst:divider_origin_selector port map(clk=>clk_line,rst=>rst_line,a0=>q_line(0),din=>bin,cout=>cinb_line,dout=>bin_line);
divider_origin_8bitadder_inst:divider_origin_8bitadder port map(clk=>clk_line,rst=>rst_line,cina=>cina_line,cinb=>cinb_line,ain=>q_line(15 downto 8),bin=>bin_line,sout=>sout_line);

process(q_line)
begin
    s<=q_line(7 downto 0);--&not sout_line(8);
    r<=cina_line&q_line(15 downto 9);
    --r<=q_line(15 downto 8);
end process;

end Behavioral;

模块:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider_origin_ctrl is
    Port (
        clk,start:in std_logic;
        clkout,rstall,done:out std_logic
     );
end divider_origin_ctrl;

architecture Behavioral of divider_origin_ctrl is

signal cnt4b:std_logic_vector(3 downto 0);

begin

process(clk,start)
begin
    rstall<=start;
    if(start='1')then cnt4b<="0000";
    elsif clk'event and clk='1'then if cnt4b<=7 then cnt4b<=cnt4b+1;end if;
    end if;
end process;

process(clk,cnt4b,start)
begin
    if (start='1')then
        clkout<='0';done<='0'; 
    elsif(start='0')then    
        if cnt4b<=7 then clkout<=clk;
        else clkout<='0';done<='1';
        end if; 
    end if;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider_origin_16bitreg is
    Port (
        clk,rst:in std_logic;
        ain:in std_logic_vector(15 downto 0);
        d:in std_logic_vector(8 downto 0);
        c_out:out std_logic;
        q:out std_logic_vector(15 downto 0)
     );
end divider_origin_16bitreg;

architecture Behavioral of divider_origin_16bitreg is

begin

process(clk,rst)
variable sr16b:std_logic_vector(15 downto 0);
begin
    if rst='1'then
        sr16b:=ain;
        c_out<=sr16b(15);--发送符号位
        sr16b(15 downto 1):=sr16b(14 downto 0);--左移一位
        sr16b(0):='0';--上0
    elsif(clk='1'and clk'event)then  
        sr16b(15 downto 8):=d(7 downto 0);
        c_out<=sr16b(15);--发送符号位
        sr16b(15 downto 1):=sr16b(14 downto 0);--左移一位
        sr16b(0):=not d(8);    --上商取反符号位
    end if;   
    q<=sr16b;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider_origin_selector is
    Port (
        clk,rst:in std_logic;
        a0:in std_logic;
        din:in std_logic_vector(7 downto 0);
        cout:out std_logic;
        dout:out std_logic_vector(7 downto 0)
     );
end divider_origin_selector;

architecture Behavioral of divider_origin_selector is

signal complement_x_negative:std_logic_vector(7 downto 0);

begin

process(din)
begin
    complement_x_negative<=(not din)+1;
end process;

process(clk,rst,a0,din)

begin
    if(rst='1')then dout<=complement_x_negative;cout<='1';
    elsif(clk'event and clk='0')then
        if(a0='1')then dout<=complement_x_negative;cout<='1';--输出加数和其符号位
        else dout<=din;cout<='0';
        end if;
    end if;    
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider_origin_8bitadder is
    Port (
        clk,rst:in std_logic;
        cina,cinb:in std_logic;
        ain,bin:in std_logic_vector(7 downto 0);
        sout:out std_logic_vector(8 downto 0)
     );
end divider_origin_8bitadder;

architecture Behavioral of divider_origin_8bitadder is
begin

process(rst,clk,ain,bin,cina,cinb)
begin
    if(rst='1')then sout<=(cina & ain)+(cinb & bin);
    elsif(clk='0')then
        sout<=(cina & ain)+(cinb & bin);
    end if;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/18 19:49:35
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity divider_origin_tb is
--  Port ( );
end divider_origin_tb;

architecture Behavioral of divider_origin_tb is
component divider_origin
    Port(
        clk,start:in std_logic;
        ain:in std_logic_vector(15 downto 0);--除数
        bin:in std_logic_vector(7 downto 0);--被除数
        done:out std_logic;

        s,r:out std_logic_vector(7 downto 0)
    );
end component;
signal clk,start: std_logic;
signal ain: std_logic_vector(15 downto 0);
signal bin: std_logic_vector(7 downto 0);
signal done: std_logic;
signal s,r: std_logic_vector(7 downto 0);
begin
divider_origin_inst:divider_origin port map(clk,start,ain,bin,done,s,r);

clock_gen:process
begin  
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

test:process
begin
    --09 0d
    ain<=x"008B";
    bin<=x"0E";
    wait for 25ns;
    start<='1';
    wait for 25ns;
    start<='0';    
    wait for 100ns;
    
    --00 ff
    ain<=x"0001";
    bin<=x"02";
    wait for 25ns;
    start<='1';
    wait for 25ns;
    start<='0';    
    wait for 100ns;
    
    --01 33
    ain<=x"00AB";
    bin<=x"78";
    wait for 25ns;
    start<='1';
    wait for 25ns;
    start<='0';    
    wait for 100ns;
    
    --ad 27
    ain<=x"ABCD";
    bin<=x"FE";
    wait for 25ns;
    start<='1';
    wait for 25ns;
    start<='0';    
    wait for 100ns;
   
    --01 01
    ain<=x"0100";
    bin<=x"FF";
    wait for 25ns;
    start<='1';
    wait for 25ns;
    start<='0';    
    wait for 100ns;
    
    wait;
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/23 21:55:51
#----------------------------------------------------------------------------------
#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]
#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {ain[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[7]}]
set_property PACKAGE_PIN C9         [get_ports {ain[0]}]
set_property PACKAGE_PIN B9         [get_ports {ain[1]}]
set_property PACKAGE_PIN G11        [get_ports {ain[2]}]
set_property PACKAGE_PIN F10        [get_ports {ain[3]}]
set_property PACKAGE_PIN D10        [get_ports {ain[4]}]
set_property PACKAGE_PIN E11        [get_ports {ain[5]}]
set_property PACKAGE_PIN D11        [get_ports {ain[6]}]
set_property PACKAGE_PIN A14        [get_ports {ain[7]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[8]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[9]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[10]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[11]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[12]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[13]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[14]}]
set_property IOSTANDARD LVCMOS18    [get_ports {ain[15]}]
set_property PACKAGE_PIN B10        [get_ports {ain[8]}]
set_property PACKAGE_PIN A10        [get_ports {ain[9]}]
set_property PACKAGE_PIN B15        [get_ports {ain[10]}]
set_property PACKAGE_PIN A15        [get_ports {ain[11]}]
set_property PACKAGE_PIN A13        [get_ports {ain[12]}]
set_property PACKAGE_PIN A12        [get_ports {ain[13]}]
set_property PACKAGE_PIN D8         [get_ports {ain[14]}]
set_property PACKAGE_PIN D9         [get_ports {ain[15]}]
#SW16~SW23
set_property IOSTANDARD LVCMOS18    [get_ports {bin[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {bin[7]}]
set_property PACKAGE_PIN F8         [get_ports {bin[0]}]
set_property PACKAGE_PIN F9         [get_ports {bin[1]}]
set_property PACKAGE_PIN H11        [get_ports {bin[2]}]
set_property PACKAGE_PIN H12        [get_ports {bin[3]}]
set_property PACKAGE_PIN G14        [get_ports {bin[4]}]
set_property PACKAGE_PIN J10        [get_ports {bin[5]}]
set_property PACKAGE_PIN H14        [get_ports {bin[6]}]
set_property PACKAGE_PIN J11        [get_ports {bin[7]}]


#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

set_property PACKAGE_PIN J8         [get_ports rst]
set_property IOSTANDARD LVCMOS18    [get_ports rst]
set_property PACKAGE_PIN J14        [get_ports start]
set_property IOSTANDARD LVCMOS18    [get_ports start]

#LED
set_property IOSTANDARD LVCMOS33 		[get_ports done]
set_property PACKAGE_PIN G16			[get_ports done]

8.指令存储器 IR 设计

 IR 功能分析

         传送指令编码到微控制器

         生成 PC 的新地址

         生成 RAM 的读写地址

 IR 功能实现

         传送指令编码到微控制器

                clk_IR 上升沿有效,LD_IR1 高电平有效, data->IR。

         寄存器地址操作 Data[0]-> RS;Data[1]->RD;

         生成 PC 的新地址

                clk_IR 上升沿有效,LD_IR2 高电平有效,data[3..0]->PC[11..8];

                clk_IR 上升沿有效,LD_IR3 高电平有效,data[7..0]->PC[7..0]。

         生成 RAM 的读写地址

                clk_IR 上升沿有效,LD_IR3 高电平有效 data[7..0]->PC[7..0];

                nARen 低电平有效, PC[6..0]->AR[6..0]。

源码:
 

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/20 10:29:36
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IR_test is
    port (
        rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen:in std_logic;
        
        RS,RD:out std_logic;--传送操作寄存器(寄存器地址)
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end IR_test;

architecture Behavioral of IR_test is
component IR
    Port (
        rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen:in std_logic;
        DATA_BUS:in std_logic_vector(7 downto 0);
        
        IR_out:out std_logic_vector(7 downto 0);--传送指令到指令寄存器
        RS,RD:out std_logic;--传送操作寄存器(寄存器地址)
        PC_out:out std_logic_vector(11 downto 0);--PC地址总线
        AR:out std_logic_vector(6 downto 0)
    );
end component;
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        sel_out:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;

signal clk_line: std_logic;
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0);
signal DATA_BUS_line :std_logic_vector(7 downto 0);
signal IR_line_line       :std_logic_vector(7 downto 0);--传送指令到指令寄存器
signal PC_out_line   :std_logic_vector(11 downto 0);--PC地址总线
signal AR_line       :std_logic_vector(6 downto 0);

begin

clk_div_inst:clk_div generic map(10000)port map(rst,clk_IR,clk_line);
sig_dis_inst:seg_dis port map(rst,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);
IR_inst:IR port map(rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen,DATA_BUS_line,IR_line_line,RS,RD,PC_out_line,AR_line);

process(DATA_BUS_line,IR_line_line,PC_out_line,AR_line)
begin
        data_in_A<="00000000"&DATA_BUS_line;
        data_in_B<="00000000"&IR_line_line;
        data_in_C<="0000"&PC_out_line;
        data_in_D<="000000000"&AR_line;
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/20 10:29:36
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IR is
    Port (
        rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen:in std_logic;
        DATA_BUS:in std_logic_vector(7 downto 0);
        
        IR_out:out std_logic_vector(7 downto 0);--传送指令到指令寄存器
        RS,RD:out std_logic;--传送操作寄存器(寄存器地址)
        PC_out:out std_logic_vector(11 downto 0);--PC地址总线
        AR:out std_logic_vector(6 downto 0)
    );
end IR;

architecture Behavioral of IR is

begin

process(rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen)
begin
    if(rst='1')then
        IR_out<=(others=>'0');
        PC_out<=(others=>'0');
        RS<='0';RD<='0';
    elsif(clk_IR='1' and clk_IR'event)then
        if(LD_IR1='1')then IR_out<=DATA_BUS;end if;
        RS<=DATA_BUS(0);RD<=DATA_BUS(1);
        if(LD_IR2='1')then PC_out(11 downto 8)<=DATA_BUS(3 downto 0);
        elsif(LD_IR3='1')then 
            PC_out(7 downto 0)<=DATA_BUS(7 downto 0);
            if(nARen='0')then AR<=DATA_BUS(6 downto 0);end if;
        end if;
    end if;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/20 10:29:36
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IR_tb is
--  Port ( );
end IR_tb;

architecture Behavioral of IR_tb is
component IR
    Port (
        rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen:in std_logic;
        DATA_BUS:in std_logic_vector(7 downto 0);
        
        IR_out:out std_logic_vector(7 downto 0);--传送指令到指令寄存器
        RS,RD:out std_logic;--传送操作寄存器(寄存器地址)
        PC_out:out std_logic_vector(11 downto 0);--PC地址总线
        AR:out std_logic_vector(6 downto 0)
    );
end component;

signal rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen,RS,RD: std_logic;
signal DATA_BUS :std_logic_vector(7 downto 0);
signal IR_line       :std_logic_vector(7 downto 0);--传送指令到指令寄存器
signal PC_out   :std_logic_vector(11 downto 0);--PC地址总线
signal AR       :std_logic_vector(6 downto 0);

begin

IR_inst:IR port map(rst=>rst,clk_IR=>clk_IR,LD_IR1=>LD_IR1,LD_IR2=>LD_IR2,LD_IR3=>LD_IR3,nARen=>nARen,DATA_BUS=>DATA_BUS,IR_out=>IR_line,RS=>RS,RD=>RD,PC_out=>PC_out,AR=>AR);

clock:process
begin
    clk_IR<='1';
    wait for 5ns;
    clk_IR<='0';
    wait for 5ns;
end process;

test:process
begin
    rst<='1';
    --DATA_BUS<=x"EE";
    DATA_BUS<="11111111";
    LD_IR1<='1';
    LD_IR2<='0';
    LD_IR3<='0';
    nARen<='1';
    wait for 25ns;
    rst<='0';
    wait for 20ns;
    DATA_BUS<=x"FA";
    LD_IR1<='0';
    LD_IR2<='1';
    LD_IR3<='0';
    nARen<='1';
    wait for 20ns;
    DATA_BUS<=x"BC";
    LD_IR1<='0';
    LD_IR2<='0';
    LD_IR3<='1';
    nARen<='0';   
    wait;
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/23 21:55:51
#----------------------------------------------------------------------------------
#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports rst]
set_property IOSTANDARD LVCMOS18    [get_ports rst]
set_property PACKAGE_PIN J14        [get_ports LD_IR1]
set_property IOSTANDARD LVCMOS18    [get_ports LD_IR1]
set_property PACKAGE_PIN H9         [get_ports LD_IR2]
set_property IOSTANDARD LVCMOS18    [get_ports LD_IR2]
set_property PACKAGE_PIN H8         [get_ports LD_IR3]
set_property IOSTANDARD LVCMOS18    [get_ports LD_IR3]
set_property PACKAGE_PIN G10        [get_ports nARen]
set_property IOSTANDARD LVCMOS18    [get_ports nARen]

#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk_IR]
set_property IOSTANDARD LVCMOS18    [get_ports clk_IR]

#LED0~1
set_property IOSTANDARD LVCMOS33 		[get_ports RS]
set_property IOSTANDARD LVCMOS33 		[get_ports RD]
set_property PACKAGE_PIN G16			[get_ports RS]
set_property PACKAGE_PIN H16 			[get_ports RD]

#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {data_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {data_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {data_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {data_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {data_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {data_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {data_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {data_in[7]}]

9.寄存器 RN 设计

RN 功能分析:

 数据锁存功能

 读写功能

         读寄存器操作

                clk_RN 上升沿有效,Ri_EN 低电平有效,读信号 RDRi 高电平有效,选择 RS 寄存器, 输出 data[7..0]。

         写寄存器操作

                clk_RN 上升沿有效,Ri_EN 低电平有效,写信号 WRRi 高电平有效,选择 RD 寄存器, data[7..0] RD 。

源码:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/20 17:36:21
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RN is
    generic(
        depth:integer:=1
    );
    Port(
        clk_RN,Ri_EN,RDRi,WRRi:in std_logic;
        RS,RD:in std_logic_vector(depth-1 downto 0);
        data_in:in std_logic_vector(7 downto 0);
        data_out:out std_logic_vector(7 downto 0)
        --DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end RN;

architecture Behavioral of RN is
type RN is array(2**depth-1 downto 0)of std_logic_vector(7 downto 0);
signal RN_in:RN;

begin

process(clk_RN)
begin
    if(Ri_EN='1')then data_out<=(others=>'Z');
    elsif(clk_RN='1'and clk_RN'event)then
        if(RDRi='1')then data_out<=RN_in(conv_integer(RS));
        elsif(WRRi='1')then RN_in(conv_integer(RD))<=data_in;
        else data_out<=(others=>'Z');
        end if;
    end if;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/22 09:34:26
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RN_tb is
--  Port ( );
end RN_tb;

architecture Behavioral of RN_tb is
component RN
    generic(
        depth:integer:=1
    );
    Port(
        clk_RN,Ri_EN,RDRi,WRRi:in std_logic;
        RS,RD:in std_logic_vector(depth-1 downto 0);
        data_in:in std_logic_vector(7 downto 0);
        data_out:out std_logic_vector(7 downto 0)
        --DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end component;

signal clk_RN,Ri_EN,RDRi,WRRi:std_logic;
signal RS,RD:std_logic_vector(0 downto 0);
signal DATA_BUS:std_logic_vector(7 downto 0);
signal data_in:std_logic_vector(7 downto 0);
signal data_out:std_logic_vector(7 downto 0);

begin

RN_inst:RN generic map(1)port map(clk_RN,Ri_EN,RDRi,WRRi,RS,RD,data_in,data_out);
--RN_inst:RN generic map(1)port map(clk_RN,Ri_EN,RDRi,WRRi,RS,RD,DATA_BUS);

clock:process
begin
    clk_RN<='1';
    wait for 5ns;
    clk_RN<='0';
    wait for 5ns;
end process;

test:process
begin
    Ri_EN<='1';
    wait for 25ns;
    Ri_EN<='0';
    
    RDRi<='0';
    WRRi<='1';
    RS<="0";
    RD<="0";
    data_in<=x"FF";
    wait for 25ns;
    
    RDRi<='0';
    WRRi<='1';
    RS<="0";
    RD<="1";
    data_in<=x"EE";
    wait for 25ns;
    
    RDRi<='1';
    WRRi<='0';
    RS<="0";
    RD<="0";
    wait for 25ns;
    
    RDRi<='1';
    WRRi<='0';
    RS<="1";
    RD<="0";
       
    wait for 25ns;
    Ri_EN<='1';
    wait;
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/23 21:55:51
#----------------------------------------------------------------------------------
#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {data_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {data_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {data_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {data_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {data_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {data_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {data_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {data_in[7]}]

#LED
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[6]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[7]}]
set_property PACKAGE_PIN G16			[get_ports {data_out[0]}]
set_property PACKAGE_PIN H16 			[get_ports {data_out[1]}]
set_property PACKAGE_PIN D16 			[get_ports {data_out[2]}]
set_property PACKAGE_PIN D15 			[get_ports {data_out[3]}]
set_property PACKAGE_PIN C18 			[get_ports {data_out[4]}]
set_property PACKAGE_PIN C17 			[get_ports {data_out[5]}]
set_property PACKAGE_PIN B19 			[get_ports {data_out[6]}]
set_property PACKAGE_PIN C19 			[get_ports {data_out[7]}]

#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk_RN]
set_property IOSTANDARD LVCMOS18    [get_ports clk_RN]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports Ri_EN]
set_property IOSTANDARD LVCMOS18    [get_ports Ri_EN]
set_property PACKAGE_PIN J14        [get_ports RDRi]
set_property IOSTANDARD LVCMOS18    [get_ports RDRi]
set_property PACKAGE_PIN H9         [get_ports WRRi]
set_property IOSTANDARD LVCMOS18    [get_ports WRRi]
set_property PACKAGE_PIN H8         [get_ports {RS[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {RS[0]}]
set_property PACKAGE_PIN G10        [get_ports {RD[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {RD[0]}]

10.ALU算术逻辑单元设计

算术逻辑单元(ALU):执行各种算术和逻辑运算。

 算术运算操作 :加、减、乘、除

 逻辑运算操作:与、或、非、异或

 ALU 输入:操作数以及来自控制单元的控制命令

 ALU 输出:运算结果,以及状态信息

源码:

顶层;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/23 12:35:51
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_test is
    port(
        clk : in std_logic; --全局时钟和ALU时钟
        nreset : in std_logic;      --全局复位信号
        M_A,M_B : in std_logic;     --暂存器控制信号
        M_F : in std_logic;         --程序状态字控制信号
        nALU_EN : in std_logic;     --alu运算结果输出使能
        nPSW_EN : in std_logic;     --psw输出使能
        C0 : in std_logic;          --进位输入
        S : in std_logic_vector(4 downto 0);        --运算类型和操作选择,M为最高位S(4),其余在低四位
        F_in : in std_logic_vector(1 downto 0);     --移位功能选择
        DATA_BUS : inout std_logic_vector(7 downto 0);  --数据总线
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end ALU_test;

architecture Behavioral of ALU_test is
component clock
    Port(
        clk,rst:in std_logic;
        clk1,nclk1:out std_logic;   --clk
        clk2,nclk2:out std_logic;   --clk二分频
        w0,w1,w2,w3:out std_logic   --节拍信号
    );
end component;
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;
component ALU 
    port(
        clk,clk_ALU : in std_logic; --全局时钟和ALU时钟
        nreset : in std_logic;      --全局复位信号
        M_A,M_B : in std_logic;     --暂存器控制信号
        M_F : in std_logic;         --程序状态字控制信号
        nALU_EN : in std_logic;     --alu运算结果输出使能
        nPSW_EN : in std_logic;     --psw输出使能
        C0 : in std_logic;          --进位输入
        S : in std_logic_vector(4 downto 0);        --运算类型和操作选择,M为最高位S(4),其余在低四位
        F_in : in std_logic_vector(1 downto 0);     --移位功能选择
        
        regA_out,regB_out,result_out:out std_logic_vector(7 downto 0);
        DATA_BUS : inout std_logic_vector(7 downto 0);  --数据总线
        AC : out std_logic;     --半进位标志
        CY : out std_logic;     --进位标志
        ZN : out std_logic;     --零标志
        OV : out std_logic      --溢出标志
    );
end component;

signal nclk2,clk_line:std_logic;
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0);
signal regA_out,regB_out,result_out:std_logic_vector(7 downto 0);

signal AC : std_logic;     --半进位标志
signal CY : std_logic;     --进位标志
signal ZN : std_logic;     --零标志
signal OV : std_logic;      --溢出标志

begin
clock_inst:clock port map(clk=>clk,rst=>nreset,nclk2=>nclk2);
clk_div_inst:clk_div generic map(10000)port map(nreset,clk,clk_line);
seg_dis_inst:seg_dis port map(nreset,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);
ALU_inst:ALU port map(clk,nclk2,nreset,m_A,m_B,m_F,nALU_EN,nPSW_EN,C0,S,F_in,regA_out,regB_out,result_out,DATA_BUS,AC,CY,ZN,OV);

process(DATA_BUS,AC,CY,ZN,OV,regA_out,regB_out,result_out)
begin
    data_in_A<="00000000"&DATA_BUS;
    data_in_B<="000"& AC & "000" & CY & "000" & ZN & "000" & OV;
    data_in_C<=regA_out&regB_out;
    data_in_D<=result_out&"00000000";
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/22 11:58:10
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
    port(
        clk,clk_ALU : in std_logic; --全局时钟和ALU时钟
        nreset : in std_logic;      --全局复位信号
        M_A,M_B : in std_logic;     --暂存器控制信号
        M_F : in std_logic;         --程序状态字控制信号
        nALU_EN : in std_logic;     --alu运算结果输出使能
        nPSW_EN : in std_logic;     --psw输出使能
        C0 : in std_logic;          --进位输入
        S : in std_logic_vector(4 downto 0);        --运算类型和操作选择,M为最高位S(4),其余在低四位
        F_in : in std_logic_vector(1 downto 0);     --移位功能选择
        
        regA_out,regB_out,result_out:out std_logic_vector(7 downto 0);
        DATA_BUS : inout std_logic_vector(7 downto 0);  --数据总线
        AC : out std_logic;     --半进位标志
        CY : out std_logic;     --进位标志
        ZN : out std_logic;     --零标志
        OV : out std_logic      --溢出标志
    );
end ALU;

architecture Behavioral of ALU is
component array_multiplier
    Port (
        clk:in std_logic;
        a_in,b_in:in std_logic_vector(7 downto 0);
        sum_out:out std_logic_vector(15 downto 0)
    );
end component;
component divider_origin
    Port(
        clk,start:in std_logic;
        ain:in std_logic_vector(15 downto 0);--除数(要求除数大于被除数!)
        bin:in std_logic_vector(7 downto 0);--被除数
        done:out std_logic;

        s,r:out std_logic_vector(7 downto 0)
    );
end component;

signal regA:std_logic_vector(8 downto 0);
signal regB:std_logic_vector(8 downto 0);
signal result:std_logic_vector(8 downto 0);
signal PSW_reg:std_logic_vector(7 downto 0);        --pws(0):CY psw(1):ZN

signal AC_signal :std_logic;
signal CY_signal :std_logic;
signal ZN_signal :std_logic;
signal OV_signal :std_logic;

signal multiplier_out:std_logic_vector(15 downto 0);
signal start,done:std_logic;
signal divider_ina:std_logic_vector(15 downto 0);
signal divider_r:std_logic_vector(7 downto 0);

begin
array_multiplier_inst:array_multiplier port map(clk_ALU,regA(7 downto 0),regB(7 downto 0),multiplier_out);
--divider_origin_inst:divider_origin port map(clk,start,divider_ina,DATA_BUS,done,result(7 downto 0),divider_r);

process(clk_ALU,nreset) 
variable count:integer:=0;
begin
    if(nreset = '1')then
        start<='1';   
        regA <= "000000000";
        regA <= "000000000";
        result <= "000000000";
        DATA_BUS <= "ZZZZZZZZ";
        AC<= '0';CY<= '0';ZN<= '0';OV<= '0';
        
    elsif(clk_ALU'event and clk_ALU = '1')then
        if(M_A='1'and M_B='0')then     --锁存到A
            regA(7 downto 0) <= DATA_BUS;
            regA(8) <= '0';
        elsif(M_A='0'and M_B='1')then     --锁存到B 
            regB(7 downto 0) <= DATA_BUS;
            regB(8) <= '0';
            
        elsif(nALU_EN = '0')then
            case S is
                when "00000" =>         --直传
                    result <= regA;
                    CY_signal <= result(8);
                when "00001" =>         --加法
                    result <= regA+regB+C0;
                    CY_signal <= result(8);
                when "00010" =>         --减法
                    result <= regA - regB;
                    CY_signal <= result(8);
                    if(regA<regB)then OV_signal<='1';end if; 
                when "00100" =>         --乘法
                    result(7 downto 0) <= multiplier_out(7 downto 0);
                    CY_signal <= regA(8)xor regB(8);
                    if(regA*regB>x"FF")then OV_signal<='1';end if; 
                when "01000" =>         --除法
                    case count is
                        when 0=>
                            divider_ina<=regA(7 downto 0)&regB(7 downto 0);
                            start<='0';
                            count:=count+1;
                        when others=>null;
                    end case;
                    CY_signal <= regA(8)xor regB(8);
                    
                when "10000" =>         --清零
                    regA <= "000000000";
                    result <= regA;
                    CY_signal <= '0';
                when "10001" =>         --与
                    result <= regA and regB;
                    CY_signal <= '0';
                when "10010" =>         --或
                    result <= regA or regB;
                    CY_signal <= '0';
                when "10100" =>         --A取非
                    result <= not regA;
                    CY_signal <= '0';
                when "11000" =>         --异或
                    result <= regA xor regB;
                    CY_signal <= '0';
                when others =>
                    result <= "000000000";
            end case;
            
            case F_in is 
                when "00" => DATA_BUS<= result(7 downto 0);--直接传送
                when "01" => DATA_BUS<= result(8 downto 1);--带C右移
                when "10" => DATA_BUS<= result(6 downto 0)&CY_signal;--循环左移
                when "11" => DATA_BUS<= result(6 downto 0)&'0';--逻辑左移
                when others => DATA_BUS<=(others=>'Z');
            end case;
            
            CY <= CY_signal;
            if(result="000000000")then ZN_signal<='1';else ZN_signal<='0';end if;
            ZN<=ZN_signal;
            
        elsif(nPSW_EN = '0')then
            PSW_reg(0) <= CY_signal;
            PSW_reg(1) <= ZN_signal;
            DATA_BUS<= PSW_reg;
        else
            DATA_BUS <= "ZZZZZZZZ";
        end if;
        
    end if;
end process;

process(regA,regB,result)
begin
    regA_out<=regA(7 downto 0);
    regB_out<=regB(7 downto 0);
    result_out<=result(7 downto 0);
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/23 13:34:13
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU_tb is
--  Port ( );
end ALU_tb;

architecture Behavioral of ALU_tb is
component ALU
    port(
        clk,clk_ALU : in std_logic; --全局时钟和ALU时钟
        nreset : in std_logic;      --全局复位信号
        M_A,M_B : in std_logic;     --暂存器控制信号
        M_F : in std_logic;         --程序状态字控制信号
        nALU_EN : in std_logic;     --alu运算结果输出使能
        nPSW_EN : in std_logic;     --psw输出使能
        C0 : in std_logic;          --进位输入
        S : in std_logic_vector(4 downto 0);        --运算类型和操作选择,M为最高位S(4),其余在低四位
        F_in : in std_logic_vector(1 downto 0);     --移位功能选择
        
        DATA_BUS : inout std_logic_vector(7 downto 0);  --数据总线
        AC : out std_logic;     --半进位标志
        CY : out std_logic;     --进位标志
        ZN : out std_logic;     --零标志
        OV : out std_logic      --溢出标志
    );
end component;

signal clk,nclk2,nreset,m_A,m_B,m_F,nALU_EN,nPSW_EN,C0:std_logic;

signal S :std_logic_vector(4 downto 0);
signal F_in :std_logic_vector(1 downto 0);     
signal DATA_BUS:std_logic_vector(7 downto 0);   
signal AC : std_logic;     --半进位标志
signal CY : std_logic;     --进位标志
signal ZN : std_logic;     --零标志
signal OV : std_logic;      --溢出标志

begin
ALU_inst:ALU port map(clk,nclk2,nreset,m_A,m_B,m_F,nALU_EN,nPSW_EN,C0,S,F_in,DATA_BUS,AC,CY,ZN,OV);

clock:process
begin
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

clock_nclk2:process
begin
    nclk2<='0';
    wait for 10ns;
    nclk2<='1';
    wait for 10ns;
end process;

test:process
begin
    nreset<='1';
    M_A<='0';
    M_B<='0';
    M_F<='0';
    nALU_EN<='1';
    nPSW_EN<='1';
    C0<='0';
    S<="10010";
    F_in<="00";
    wait for 25ns;
    
    nreset<='0';
    DATA_BUS<=X"04";
    M_A<='1';
    M_B<='0';
    wait for 25ns;
    DATA_BUS<=X"02";
    M_A<='0';
    M_B<='1';
    wait for 25ns;
--    DATA_BUS<="ZZZZZZZZ";
    M_A<='0';
    M_B<='0';
    nALU_EN<='0';
    wait for 50ns;
    
    nALU_EN<='1';
    nPSW_EN<='0';
    wait;
    
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/23 21:55:51
#----------------------------------------------------------------------------------
#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[7]}]
set_property PACKAGE_PIN C9         [get_ports {DATA_BUS[0]}]
set_property PACKAGE_PIN B9         [get_ports {DATA_BUS[1]}]
set_property PACKAGE_PIN G11        [get_ports {DATA_BUS[2]}]
set_property PACKAGE_PIN F10        [get_ports {DATA_BUS[3]}]
set_property PACKAGE_PIN D10        [get_ports {DATA_BUS[4]}]
set_property PACKAGE_PIN E11        [get_ports {DATA_BUS[5]}]
set_property PACKAGE_PIN D11        [get_ports {DATA_BUS[6]}]
set_property PACKAGE_PIN A14        [get_ports {DATA_BUS[7]}]

#sw31~23
set_property PACKAGE_PIN J8         [get_ports nreset]
set_property IOSTANDARD LVCMOS18    [get_ports nreset]
set_property PACKAGE_PIN J14        [get_ports nALU_EN]
set_property IOSTANDARD LVCMOS18    [get_ports nALU_EN]
set_property PACKAGE_PIN H9         [get_ports nPSW_EN]
set_property IOSTANDARD LVCMOS18    [get_ports nPSW_EN]
set_property PACKAGE_PIN H8         [get_ports M_A]
set_property IOSTANDARD LVCMOS18    [get_ports M_A]
set_property PACKAGE_PIN G10        [get_ports M_B]
set_property IOSTANDARD LVCMOS18    [get_ports M_B]
set_property PACKAGE_PIN G9         [get_ports M_F]
set_property IOSTANDARD LVCMOS18    [get_ports M_F]
set_property PACKAGE_PIN J13        [get_ports C0]
set_property IOSTANDARD LVCMOS18    [get_ports C0]

#SW16~20
set_property IOSTANDARD LVCMOS18    [get_ports {S[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {S[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {S[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {S[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {S[4]}]
set_property PACKAGE_PIN F8         [get_ports {S[0]}]
set_property PACKAGE_PIN F9         [get_ports {S[1]}]
set_property PACKAGE_PIN H11        [get_ports {S[2]}]
set_property PACKAGE_PIN H12        [get_ports {S[3]}]
set_property PACKAGE_PIN G14        [get_ports {S[4]}]

#SW22~23
set_property IOSTANDARD LVCMOS18    [get_ports {F_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {F_in[1]}]
set_property PACKAGE_PIN H14        [get_ports {F_in[0]}]
set_property PACKAGE_PIN J11        [get_ports {F_in[1]}]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

11.数据存储器 RAM 设计

高电平写操作有效,低电平读有效。其中 clk_RAM=nclk1 & W1,在组建 CPU 模块时使用。

1)读数据操作:clk_RAM 上升沿有效,RAM_CS 高电平,wr_nRD 低电平,nRAM_EN 低 电平,[AR] -> data 。

2)写数据操作:clk_RAM 上升沿有效,RAM_CS 高电平,wr_nRD 高电平有效,data->[AR]。

源码:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/23 21:55:51
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM is
    generic(
        depth:integer:=7;
        width:integer:=8
        );
    port( 
        clk_RAM:in STD_LOGIC;       --RAM时钟信号
        n_reset:in STD_LOGIC;       --RAM选择信号
        RAM_CS:in STD_LOGIC;        --RAM片选信号
        nRAM_EN:in STD_LOGIC;       --RAM输出使能
        Wr_nRD :in STD_LOGIC;       --RAM读写信号
        AR:in STD_LOGIC_VECTOR (depth-1 downto 0);  --RAM地址信号
        
        --DATA_BUS: inout STD_LOGIC_VECTOR (width-1 downto 0) --数据总线
        data_in:in STD_LOGIC_VECTOR (width-1 downto 0);
        data_out:out STD_LOGIC_VECTOR (width-1 downto 0)
        );
end RAM;

architecture Behavioral of RAM is

type ram_array is array(0 to 2**depth) of STD_LOGIC_VECTOR (width-1 downto 0);
signal index : integer range 0 to 2**depth;
signal SRAM:ram_array;

begin

process (n_reset,clk_RAM) 
begin
    index<=conv_integer(AR);
    if(n_reset='1')  then 
        --DATA_BUS<=(others=>'Z');
        data_out<=(others=>'Z');
    elsif(clk_RAM'event and clk_RAM='1') then
        if(RAM_CS='1')then
            if(Wr_nRD='1')then
                --SRAM(index)<=DATA_BUS;
                SRAM(index)<=data_in;
            elsif(nRAM_EN='0')then
                --DATA_BUS<=SRAM(index);
                data_out<=SRAM(index);
            else
                --DATA_BUS<=(others=>'Z');
                data_out<=(others=>'Z');
            end if;
        else 
            --DATA_BUS<=(others=>'Z');
            data_out<=(others=>'Z');
        end if;
    end if;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/23 21:55:51
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM_tb is
--  Port ( );
end RAM_tb;

architecture Behavioral of RAM_tb is
component RAM
    generic(
        depth:positive:=7;
        width:positive:=8
    );
    Port (
        clk_RAM:in STD_LOGIC;       --RAM时钟信号
        n_reset:in STD_LOGIC;       --RAM选择信号
        RAM_CS:in STD_LOGIC;        --RAM片选信号
        nRAM_EN:in STD_LOGIC;       --RAM输出使能
        Wr_nRD :in STD_LOGIC;       --RAM读写信号
        AR:in STD_LOGIC_VECTOR (depth-1 downto 0);  --RAM地址信号
        
        DATA_BUS: inout STD_LOGIC_VECTOR (width-1 downto 0) --数据总线
        --data_in:in STD_LOGIC_VECTOR (width-1 downto 0);
        --data_out:out STD_LOGIC_VECTOR (width-1 downto 0))
    );
end component;

signal clk_RAM,n_reset,RAM_CS,nRAM_EN,Wr_nRD:std_logic;
signal AR:std_logic_vector(6 downto 0);
signal DATA_BUS:std_logic_vector(7 downto 0);
signal data_in,data_out:std_logic_vector(7 downto 0);

begin

RAM_inst:RAM generic map(7,8)port map(clk_RAM=>clk_RAM,n_reset=>n_reset,RAM_CS=>RAM_CS,nRAM_EN=>nRAM_EN,Wr_nRD=>Wr_nRD,AR=>AR,DATA_BUS=>DATA_BUS);
--RAM_inst:RAM generic map(7,8)port map(clk_RAM=>clk_RAM,n_reset=>n_reset,RAM_CS=>RAM_CS,nRAM_EN=>nRAM_EN,Wr_nRD=>Wr_nRD,AR=>AR,data_in=>data_in,data_out=>data_out);

clock:process
begin
    clk_RAM<='1';
    wait for 5ns;
    clk_RAM<='0';
    wait for 5ns;
end process;

test:process
begin
    n_reset<='1';
    wait for 25ns;
    n_reset<='0';
    
    RAM_CS<='1';
    nRAM_EN<='1';
    Wr_nRD<='1';
    AR<="0000000";
    wait for 25ns;
    DATA_BUS<=x"FF";
    wait for 25ns;
    AR<="0000001";
    wait for 25ns;
    DATA_BUS<=x"EE";
    wait for 25ns;
    
    nRAM_EN<='0';
    Wr_nRD<='0';
    AR<="0000000";
    wait for 25ns;
    AR<="0000001";
    
    wait;

end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/23 21:55:51
#----------------------------------------------------------------------------------
#sw0~6
set_property IOSTANDARD LVCMOS18 [get_ports {AR[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {AR[6]}]
set_property PACKAGE_PIN C9 [get_ports {AR[0]}]
set_property PACKAGE_PIN B9 [get_ports {AR[1]}]
set_property PACKAGE_PIN G11 [get_ports {AR[2]}]
set_property PACKAGE_PIN F10 [get_ports {AR[3]}]
set_property PACKAGE_PIN D10 [get_ports {AR[4]}]
set_property PACKAGE_PIN E11 [get_ports {AR[5]}]
set_property PACKAGE_PIN D11 [get_ports {AR[6]}]

#LED
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {DATA_BUS[7]}]
#set_property PACKAGE_PIN G16 [get_ports {DATA_BUS[0]}]
#set_property PACKAGE_PIN H16 [get_ports {DATA_BUS[1]}]
#set_property PACKAGE_PIN D16 [get_ports {DATA_BUS[2]}]
#set_property PACKAGE_PIN D15 [get_ports {DATA_BUS[3]}]
#set_property PACKAGE_PIN C18 [get_ports {DATA_BUS[4]}]
#set_property PACKAGE_PIN C17 [get_ports {DATA_BUS[5]}]
#set_property PACKAGE_PIN B19 [get_ports {DATA_BUS[6]}]
#set_property PACKAGE_PIN C19 [get_ports {DATA_BUS[7]}]

#sw31
set_property PACKAGE_PIN J8 [get_ports n_reset]
set_property IOSTANDARD LVCMOS18 [get_ports n_reset]

#sw30~28
set_property PACKAGE_PIN J14 [get_ports RAM_CS]
set_property IOSTANDARD LVCMOS18 [get_ports RAM_CS]
set_property PACKAGE_PIN H9         [get_ports nRAM_EN]
set_property IOSTANDARD LVCMOS18    [get_ports nRAM_EN]
set_property PACKAGE_PIN H8         [get_ports Wr_nRD]
set_property IOSTANDARD LVCMOS18    [get_ports Wr_nRD]

#clk
set_property PACKAGE_PIN E10 [get_ports clk_RAM]
set_property IOSTANDARD LVCMOS18 [get_ports clk_RAM]

#LED
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[6]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {data_out[7]}]
set_property PACKAGE_PIN G16			[get_ports {data_out[0]}]
set_property PACKAGE_PIN H16 			[get_ports {data_out[1]}]
set_property PACKAGE_PIN D16 			[get_ports {data_out[2]}]
set_property PACKAGE_PIN D15 			[get_ports {data_out[3]}]
set_property PACKAGE_PIN C18 			[get_ports {data_out[4]}]
set_property PACKAGE_PIN C17 			[get_ports {data_out[5]}]
set_property PACKAGE_PIN B19 			[get_ports {data_out[6]}]
set_property PACKAGE_PIN C19 			[get_ports {data_out[7]}]

set_property IOSTANDARD LVCMOS18    [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[7]}]
set_property PACKAGE_PIN B10        [get_ports {data_in[0]}]
set_property PACKAGE_PIN A10        [get_ports {data_in[1]}]
set_property PACKAGE_PIN B15        [get_ports {data_in[2]}]
set_property PACKAGE_PIN A15        [get_ports {data_in[3]}]
set_property PACKAGE_PIN A13        [get_ports {data_in[4]}]
set_property PACKAGE_PIN A12        [get_ports {data_in[5]}]
set_property PACKAGE_PIN D8         [get_ports {data_in[6]}]
set_property PACKAGE_PIN D9         [get_ports {data_in[7]}]

12.堆栈指针 SP 设计

其中 clk_SP=nclk2,在组建 CPU 模块时使用。

1)数据存储功能:clk_SP 上升沿有效,SP_CS 高电平,nSP_EN 高电平,data->SP。

2)加 1 功能:clk_SP 上升沿有效,SP_CS 高电平,SP_UP 高电平,nSP_EN 低电平有效,SP+1->SP,SP->AR。

3)减 1 功能:clk_SP 上升沿有效,SP_CS 高电平,SP_DN 高电平,nSP_EN 低电平有效, SP-1->SP,SP->AR。

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 13:45:37
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SP_test is
    Port(
        clk:in std_logic;       --时钟信号
        nreset:in std_logic;    --复位信号                
        SP_CS:in std_logic;     --SP选择信号
        SP_UP:in std_logic;     --SP+1控制
        SP_DN:in std_logic;     --SP-1控制
        nSP_EN:in std_logic;    --SP输出使能
        key_in:in std_logic;    --按键时钟
        
        AR:out std_logic_vector(6 downto 0);--SP指向RAM地址
        --data_in:in std_logic_vector(7 downto 0);
        --data_out:out std_logic_vector(7 downto 0)
        DATA_BUS:inout std_logic_vector(7 downto 0)   --数据总线
    );
end SP_test;

architecture Behavioral of SP_test is
component SP
    Port(
        clk_SP:in std_logic;    --SP时钟信号
        nreset:in std_logic;    --复位信号                
        SP_CS:in std_logic;     --SP选择信号
        SP_UP:in std_logic;     --SP+1控制
        SP_DN:in std_logic;     --SP-1控制
        nSP_EN:in std_logic;    --SP输出使能
        
        AR:out std_logic_vector(6 downto 0);--SP指向RAM地址
        --data_in:in std_logic_vector(7 downto 0);
        --data_out:out std_logic_vector(7 downto 0)
        DATA_BUS:inout std_logic_vector(7 downto 0)   --数据总线
    );
end component;
component key_stroke
    generic(CLK_FRE:integer:=100000000);
    Port (
        clk:in std_logic;
        reset:in std_logic;
        key_in:in std_logic;
        output:out std_logic           
    );
end component;

signal clk_line:STD_LOGIC;

begin

key_stroke_inst:key_stroke generic map(100000000)port map(clk,nreset,key_in,clk_line);
SP_inst:SP PORT MAP(clk_line,nreset,SP_CS,SP_UP,SP_DN,nSP_EN,AR,DATA_BUS);


end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 10:52:17
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SP is
    Port(
        clk_SP:in std_logic;    --SP时钟信号
        nreset:in std_logic;    --复位信号                
        SP_CS:in std_logic;     --SP选择信号
        SP_UP:in std_logic;     --SP+1控制
        SP_DN:in std_logic;     --SP-1控制
        nSP_EN:in std_logic;    --SP输出使能
        
        AR:out std_logic_vector(6 downto 0);--SP指向RAM地址
        --data_in:in std_logic_vector(7 downto 0);
        --data_out:out std_logic_vector(7 downto 0)
        DATA_BUS:inout std_logic_vector(7 downto 0)   --数据总线
    );
end SP;

architecture Behavioral of SP is

signal SP_p:std_logic_vector(6 downto 0);--指向RAM地址

begin

process(clk_SP,nreset)
begin   
    if(nreset='0')then AR<=(others=>'Z');
    elsif(clk_SP='1'and clk_SP'event)then
        if(SP_CS='1')then
            if(nSP_EN='1')then 
                --SP_p<=data_in;
                SP_p<=DATA_BUS(6 downto 0);
            else
                if(SP_UP='1'and SP_DN='0')then SP_p<=SP_p+1;
                elsif(SP_UP='0'and SP_DN='1')then SP_p<=SP_p-1;
                end if;
                --data_out<=SP_p;
                AR<=SP_p;
            end if;
        else AR<=(others=>'Z');
        end if;
    end if;
end process;

end Behavioral;

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 13:29:19
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SP_tb is
--  Port ( );
end SP_tb;

architecture Behavioral of SP_tb is
component SP
    Port(
        clk_SP:in std_logic;    --SP时钟信号
        nreset:in std_logic;    --复位信号                
        SP_CS:in std_logic;     --SP选择信号
        SP_UP:in std_logic;     --SP+1控制
        SP_DN:in std_logic;     --SP-1控制
        nSP_EN:in std_logic;    --SP输出使能
        
        AR:out std_logic_vector(6 downto 0);--SP指向RAM地址
        --data_in:in std_logic_vector(7 downto 0);
        --data_out:out std_logic_vector(7 downto 0)
        DATA_BUS:inout std_logic_vector(7 downto 0)   --数据总线
    );
end component;

signal clk_SP,nreset,SP_CS,SP_UP,SP_DN,nSP_EN:STD_LOGIC;
signal AR:std_logic_vector(6 downto 0);
signal DATA_BUS:std_logic_vector(7 downto 0);

begin

SP_inst:SP PORT MAP(clk_SP,nreset,SP_CS,SP_UP,SP_DN,nSP_EN,AR,DATA_BUS);

clock:process
begin
    clk_SP<='1';
    wait for 5ns;
    clk_SP<='0';
    wait for 5ns;
end process;

test:process
begin
    nreset<='0';
    SP_CS<='1';
    SP_UP<='0';
    SP_DN<='0';
    nSP_EN<='1';
    DATA_BUS<="ZZZZZZZZ";
    wait for 25ns;
    
    DATA_BUS<=x"0F";
    nreset<='1';
    wait for 25ns;
    
    SP_UP<='1';
    SP_DN<='0';
    nSP_EN<='0';
    wait for 25ns;
    
    SP_UP<='1';
    SP_DN<='0';
    nSP_EN<='0';
    wait for 25ns;
    
    SP_UP<='0';
    SP_DN<='1';
    nSP_EN<='0';
    wait for 25ns;
    
    wait;
    
end process;

end Behavioral;

xdc:

#clk
set_property PACKAGE_PIN E10 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports clk]

#sw31~28
set_property PACKAGE_PIN J8 [get_ports nreset]
set_property IOSTANDARD LVCMOS18 [get_ports nreset]
set_property PACKAGE_PIN J14        [get_ports SP_CS]
set_property IOSTANDARD LVCMOS18    [get_ports SP_CS]
set_property PACKAGE_PIN H9         [get_ports key_in]
set_property IOSTANDARD LVCMOS18    [get_ports key_in]
set_property PACKAGE_PIN H8         [get_ports nSP_EN]
set_property IOSTANDARD LVCMOS18    [get_ports nSP_EN]
set_property PACKAGE_PIN G10        [get_ports SP_UP ]
set_property IOSTANDARD LVCMOS18    [get_ports SP_UP ]
set_property PACKAGE_PIN G9         [get_ports SP_DN ]
set_property IOSTANDARD LVCMOS18    [get_ports SP_DN ]

#LED0~6
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[0]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[1]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[2]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[3]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[4]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[5]}]
set_property IOSTANDARD LVCMOS33 		[get_ports {AR[6]}]
set_property PACKAGE_PIN G16			[get_ports {AR[0]}]
set_property PACKAGE_PIN H16 			[get_ports {AR[1]}]
set_property PACKAGE_PIN D16 			[get_ports {AR[2]}]
set_property PACKAGE_PIN D15 			[get_ports {AR[3]}]
set_property PACKAGE_PIN C18 			[get_ports {AR[4]}]
set_property PACKAGE_PIN C17 			[get_ports {AR[5]}]
set_property PACKAGE_PIN B19 			[get_ports {AR[6]}]

#SW0~7
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {DATA_BUS[7]}]
set_property PACKAGE_PIN C9         [get_ports {DATA_BUS[0]}]
set_property PACKAGE_PIN B9         [get_ports {DATA_BUS[1]}]
set_property PACKAGE_PIN G11        [get_ports {DATA_BUS[2]}]
set_property PACKAGE_PIN F10        [get_ports {DATA_BUS[3]}]
set_property PACKAGE_PIN D10        [get_ports {DATA_BUS[4]}]
set_property PACKAGE_PIN E11        [get_ports {DATA_BUS[5]}]
set_property PACKAGE_PIN D11        [get_ports {DATA_BUS[6]}]
set_property PACKAGE_PIN A14        [get_ports {DATA_BUS[7]}]

13.采用硬件描述语言语言设计 IO 模块

其中 clk_P0=nclk2,在组建 CPU 模块时使用。

1)输入锁存:

        clk_PO 上升沿有效,P0_CS 高电平,P0_IEN 低电平,

        P0_IN-> 暂存器,RIEN 低电平, 暂存器 ->数据总线(data)。

2)输出锁存:

        clk_PO 上升沿有效,P0_CS 高电平,P0_OEN 低电平,

        数据总线(data)->暂存器,ROEN 低电平,暂存器 ->P0_OUT。

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 14:37:22
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IO_test is
    Port(
        clk:in std_logic;    --IO时钟信号
        nreset:in std_logic;    --IO复位信号
        IO_CS:in std_logic;     --IO选择信号
        IO_IEN:in std_logic;    --IO输入使能
        IO_OEN:in std_logic;    --IO输出使能
        RI_EN:in std_logic;     --IO缓存器输入使能
        RO_EN:in std_logic;     --IO缓存器输出使能
        IO_in:in std_logic_vector(7 downto 0);          --IO输入
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end IO_test;

architecture Behavioral of IO_test is

component IO
    Port(
        clk_IO:in std_logic;    --IO时钟信号
        nreset:in std_logic;    --IO复位信号
        IO_CS:in std_logic;     --IO选择信号
        IO_IEN:in std_logic;    --IO输入使能
        IO_OEN:in std_logic;    --IO输出使能
        RI_EN:in std_logic;     --IO缓存器输入使能
        RO_EN:in std_logic;     --IO缓存器输出使能
        IO_in:in std_logic_vector(7 downto 0);          --IO输入
        
        IO_out:out std_logic_vector(7 downto 0);        --IO输出
        DATA_BUS:inout std_logic_vector(7 downto 0)    --数据总线
    );
end component;
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;

signal clk_line,rst_seg:std_logic;
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0); 
signal IO_out,DATA_BUS:std_logic_vector(7 downto 0);

begin

IO_inst:IO port map(clk,nreset,IO_CS,IO_IEN,IO_OEN,RI_EN,RO_EN,IO_in,IO_out,DATA_BUS);
clk_div_inst:clk_div generic map(10000)port map(nreset,clk,clk_line);
seg_dis_inst:seg_dis port map(nreset,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);

process(IO_in,IO_out,DATA_BUS)
begin
    data_in_A<="00000000"&IO_in;
    data_in_B<="00000000"&DATA_BUS;
    data_in_C<="00000000"&IO_out;
    data_in_D<="0000000000000000";
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: 
-- Create Date: 2024/04/24 14:06:31
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IO is
    Port(
        clk_IO:in std_logic;    --IO时钟信号
        nreset:in std_logic;    --IO复位信号
        IO_CS:in std_logic;     --IO选择信号
        IO_IEN:in std_logic;    --IO输入使能
        IO_OEN:in std_logic;    --IO输出使能
        RI_EN:in std_logic;     --IO缓存器输入使能
        RO_EN:in std_logic;     --IO缓存器输出使能
        IO_in:in std_logic_vector(7 downto 0);          --IO输入
        
        IO_out:out std_logic_vector(7 downto 0);        --IO输出
        DATA_BUS:inout std_logic_vector(7 downto 0)    --数据总线
    );
end IO;

architecture Behavioral of IO is
signal reg:std_logic_vector(7 downto 0);
begin

process(nreset,clk_IO)
begin
    if(nreset='0')then IO_out<="ZZZZZZZZ";DATA_BUS<="ZZZZZZZZ";
    elsif(clk_IO='1'and clk_IO'event)then
        if(IO_CS='1')then
            if(IO_IEN='0')then 
                reg<=IO_in;
                if(RI_EN='0')then DATA_BUS<=reg;end if;
            elsif(IO_OEN='0')then 
                reg<=DATA_BUS;
                if(RO_EN='0')then IO_out<=reg;END IF;
            end if; 
        else IO_out<="ZZZZZZZZ";DATA_BUS<="ZZZZZZZZ";
        end if;
    end if;
end process;

end Behavioral;

xdc:

#----------------------------------------------------------------------------------
#-- Engineer: switch_swq
#-- Create Date: 2024/04/24 15:50:00
#----------------------------------------------------------------------------------
#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#SW0~7
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IO_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {IO_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {IO_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {IO_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {IO_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {IO_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {IO_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {IO_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {IO_in[7]}]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports nreset]
set_property IOSTANDARD LVCMOS18    [get_ports nreset]
set_property PACKAGE_PIN J14        [get_ports IO_CS]
set_property IOSTANDARD LVCMOS18    [get_ports IO_CS]
set_property PACKAGE_PIN H9         [get_ports IO_IEN]
set_property IOSTANDARD LVCMOS18    [get_ports IO_IEN]
set_property PACKAGE_PIN H8         [get_ports IO_OEN]
set_property IOSTANDARD LVCMOS18    [get_ports IO_OEN]
set_property PACKAGE_PIN G10        [get_ports RI_EN]
set_property IOSTANDARD LVCMOS18    [get_ports RI_EN]
set_property PACKAGE_PIN G9         [get_ports RO_EN]
set_property IOSTANDARD LVCMOS18    [get_ports RO_EN]


14.微控制器设计

微程序控制器基本原理:

        1)将指令分解为基本的微命令序列,把操作控制信号编制成微指令,存放到控制存储器 (CM)。

        2)运行时,从控存中取出微指令,产生指令运行所需的操作控制信号。

微程序控制器基本结构:

 控制存储器 CM --存放微程序

 微指令寄存器 µIR --存放现行微指令

 微地址形成电路--提供下一条微地址

 微地址寄存器 µAR--存放现在微地址

控制信号设计:

        • 39 条控制信号(39 位编码)

        • 27 条指令(5 位编码)->8 位微地址

其中 clk_MC=clk2 & W0,在组建 CPU 模块时使用。

源码:

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/25 16:09:02
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uC_test is
    Port(
        clk:in std_logic;    --微程序控制器时钟信号
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;      --微地址控制信号
        IR:in std_logic_vector(7 downto 2); --IR操作码信息
        CMROM_CS:in std_logic;  --控制存储器选通信号
        
        seg_dig : out std_logic_vector(15 downto 0);
        seg_data : out std_logic_vector(7 downto 0)
    );
end uC_test;

architecture Behavioral of uC_test is
component uC
    Port(
        clk_uC:in std_logic;    --微程序控制器时钟信号
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;      --微地址控制信号
        IR:in std_logic_vector(7 downto 2); --IR操作码信息
        CMROM_CS:in std_logic;  --控制存储器选通信号
        
        CM:out std_logic_vector(47 downto 8)    --控制信号输出
    );
end component;
component clock
    Port(
        clk,rst:in std_logic;
        clk1,nclk1:out std_logic;   --clk
        clk2,nclk2:out std_logic;   --clk二分频
        w0,w1,w2,w3:out std_logic   --节拍信号
    );
end component;
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;

signal clk_line,clk_line2,clk_uC,clk2,w0:std_logic;
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0); 
signal CM_line:std_logic_vector(47 downto 8);

begin

uC_inst:uC port map(clk_uC,nreset,M_uA,IR,CMROM_CS,CM_line);
clock_inst:clock port map(clk=>clk_line2,rst=>nreset,clk2=>clk2,w0=>w0);
clk_div_inst:clk_div generic map(10000)port map(nreset,clk,clk_line);
clk_div_inst2:clk_div generic map(10000000)port map(nreset,clk,clk_line2);
seg_dis_inst:seg_dis port map(nreset,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);

process(clk2,w0)
begin
    clk_uC<=clk2 and w0;
end process;

process(IR,CM_line)
begin
    data_in_A<="0000000000"&IR;
    data_in_B<=CM_line(15 downto 8)&"00000000";
    data_in_C<=CM_line(31 downto 16);
    data_in_D<=CM_line(47 downto 32);
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 16:22:50
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uC is
    Port(
        clk_uC:in std_logic;    --微程序控制器时钟信号
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;      --微地址控制信号
        IR:in std_logic_vector(7 downto 2); --IR操作码信息
        CMROM_CS:in std_logic;  --控制存储器选通信号
        
        CM:out std_logic_vector(47 downto 8)    --控制信号输出
    );
end uC;

architecture Behavioral of uC is
component uC_uA
    Port(
        clk:in std_logic;
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;
        IR:in std_logic_vector(7 downto 2);     --IR操作码信息
        uA_in:in std_logic_vector(7 downto 0);  --uIR传送的微地址
        
        uA_out:out std_logic_vector(7 downto 0) --下一条微指令的地址
    );
end component;
component uC_uAR
    Port(
        clk:in std_logic;
        nreset: in std_logic;
        uAR_in:in std_logic_vector(7 downto 0);  --uA传送的微地址
        
        uAR_out:out std_logic_vector(7 downto 0) --送至uCM的地址
    );
end component;
component uC_CM
    generic(
        width:integer := 48;    --位宽
        depth:integer := 8      --深度
    );
    port(
        clk:in std_logic;
        addr:in std_logic_vector(depth-1 downto 0);     ----uC_ROM地址
        CMROM_CS:in std_logic;  --uC_ROM输出使能
        
        data_out:out std_logic_vector(width-1 downto 0) --uC_ROM输出
    );
end component;
component uC_uIR
  Port (
    clk:in std_logic;
    CM:in std_logic_vector(47 downto 0);
    
    uA:out std_logic_vector(7 downto 0);
    uI:out std_logic_vector(47 downto 8)
  );
end component;

signal uA_in,uA_out,uAR_out:std_logic_vector(7 downto 0); 
signal CM_line:std_logic_vector(47 downto 0);

begin

uC_uA_inst:uC_uA port map(clk_uC,nreset,M_uA,IR,uA_in,uA_out);
uC_uAR_inst:uC_uAR port map(clk_uC,nreset,uA_out,uAR_out);
uC_uCM_inst:uC_CM generic map(48,8)port map(clk_uC,uAR_out,CMROM_CS,CM_line);
uC_uIR_inst:uC_uIR port map(clk_uC,CM_line,uA_in,CM);

end Behavioral;

  模块:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 16:22:50
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;

entity uC_CM is
    generic(
        width:integer := 48;    --位宽
        depth:integer := 8      --深度
    );
    port(
        clk:in std_logic;
        addr:in std_logic_vector(depth-1 downto 0);     ----uC_ROM地址
        CMROM_CS:in std_logic;  --uC_ROM输出使能
        
        data_out:out std_logic_vector(width-1 downto 0) --uC_ROM输出
    );
end uC_CM;

architecture Behavioral of uC_CM is

type matrix is array(integer range<>) of std_logic_vector(width-1 downto 0);
signal uC_ROM : matrix(0 to 2**depth-1);

procedure load_rom(signal data_word:out matrix) is 
    file romfile:text open read_mode is "uC_ROM.txt";
    variable lbuf:line;
    variable i:integer := 0; --循环变量
    variable fdata:std_logic_vector(width-1 downto 0);
begin
    while(not endfile(romfile) and i<2**depth) loop
        readline(romfile,lbuf); -- 逐行读数据
        read(lbuf,fdata); -- 将行数据保存到变量fdata
        data_word(i)<=fdata; -- 将fdata保存到内存信号量中
        i := i+1;
    end loop;
end procedure;

begin

load_rom(uC_ROM);
data_out <= uC_ROM(conv_integer(addr)) when CMROM_CS='1'else(others=>'0');

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 16:22:50
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uC_uA is
    Port(
        clk:in std_logic;
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;
        IR:in std_logic_vector(7 downto 2);     --IR操作码信息
        uA_in:in std_logic_vector(7 downto 0);  --uIR传送的微地址
        
        uA_out:out std_logic_vector(7 downto 0) --下一条微指令的地址
    );
end uC_uA;

architecture Behavioral of uC_uA is

begin

process(clk,nreset)
begin
    if(nreset='0')then uA_out<=(others=>'0');
    elsif(clk='1'and clk'event)then
        if(M_uA='1')then uA_out<=IR&"00";
        else uA_out<=uA_in;
        end if;
    end if;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 16:22:50
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uC_uAR is
    Port(
        clk:in std_logic;
        nreset: in std_logic;
        uAR_in:in std_logic_vector(7 downto 0);  --uA传送的微地址
        
        uAR_out:out std_logic_vector(7 downto 0) --送至uCM的地址
    );
end uC_uAR;

architecture Behavioral of uC_uAR is

begin

process(clk,nreset)
begin
    if(nreset='0')then uAR_out<=(others=>'0');
    elsif(clk='1'and clk'event)then uAR_out<=uAR_in;
    end if;
end process;

end Behavioral;
----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/24 16:22:50
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uC_uIR is
  Port (
    clk:in std_logic;
    CM:in std_logic_vector(47 downto 0);
    
    uA:out std_logic_vector(7 downto 0);
    uI:out std_logic_vector(47 downto 8)
  );
end uC_uIR;

architecture Behavioral of uC_uIR is

begin

uA<=CM(7 downto 0);
uI<=CM(47 downto 8);

end Behavioral;

 uC_ROM.txt:

100000000000000000000000000000000000000000000001
010000000000000000000000000000000000000000000010
001000000000000000000000000000000000000000000011
000100000000000000000000000000000000000000000100
000010000000000000000000000000000000000000000101
000001000000000000000000000000000000000000000110
000000100000000000000000000000000000000000000111
000000010000000000000000000000000000000000000000

xdc:

#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]

#SW0~15
set_property IOSTANDARD LVCMOS18    [get_ports {IR[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IR[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IR[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IR[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IR[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {IR[7]}]
set_property PACKAGE_PIN G11        [get_ports {IR[2]}]
set_property PACKAGE_PIN F10        [get_ports {IR[3]}]
set_property PACKAGE_PIN D10        [get_ports {IR[4]}]
set_property PACKAGE_PIN E11        [get_ports {IR[5]}]
set_property PACKAGE_PIN D11        [get_ports {IR[6]}]
set_property PACKAGE_PIN A14        [get_ports {IR[7]}]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports nreset]
set_property IOSTANDARD LVCMOS18    [get_ports nreset]
set_property PACKAGE_PIN J14         [get_ports CMROM_CS]
set_property IOSTANDARD LVCMOS18    [get_ports CMROM_CS]
set_property PACKAGE_PIN H9        [get_ports M_uA]
set_property IOSTANDARD LVCMOS18    [get_ports M_uA]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

15.8 位 SOC 综合设计

根据以上所设计的功能模块连接成完整的 8 位 SOC 结构。

模块修改记录:

SOC:
修改PC/ROM
*修改各模块时钟
修改各模块总线输出时机提高片选及使能优先级,并加入到敏感检测列表
修改uC使能:M_uA和CMROM_CS低电平有效(根据指令知)
uC输入输出冲突,同时输入输出控制信号
修改微指令34H:IO_CS位
修改微指令38H:IO_CS位
修改微指令24H:Ri_EN错误
修改微指令8AH:M_PC位
修改微指令65H: RDRi位
PC不再产生nPCL和nPCH信号并修改PC模块
ADD微程序增加一条微指令

源码:

顶层测试:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/27 20:08:24
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CPU_test is
    generic(
        CLK_FRE:integer:=100000000
    );
    Port(
        clk:in std_logic;
        nreset:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end CPU_test;

architecture Behavioral of CPU_test is
component CPU
    generic(
        CLK_FRE:integer:=100000000
    );
    Port(
        clk:in std_logic;
        nreset:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        
        regA_out,regB_out,result_out:out std_logic_vector(7 downto 0);
        data_out:out std_logic_vector(7 downto 0)
    );
end component;
component clk_div
    generic(
        DIV_NUM:integer:=10000
    );
    Port (
        rst:in std_logic;
        clk_in:in std_logic;
        clk_out:out std_logic
    );
end component;
component seg_dis
    port(
        rst,clk:in std_logic;
        data_in_A,data_in_B,data_in_C,data_in_D:in std_logic_vector(15 downto 0);
        
        seg_dig:out std_logic_vector(15 downto 0);
        seg_data:out std_logic_vector(7 downto 0)--管脚连接顺序:dp,g,f,e,d,c,b,a
    );
end component;
signal clk_line:std_logic;
signal data_in_A,data_in_B,data_in_C,data_in_D:std_logic_vector(15 downto 0);
signal regA_out,regB_out,result_out,data_out:std_logic_vector(7 downto 0);
begin
clk_div_inst:clk_div generic map(1000000)port map(nreset,clk,clk_line);
seg_dis_inst:seg_dis port map(nreset,clk_line,data_in_A,data_in_B,data_in_C,data_in_D,seg_dig,seg_data);
CPU_inst:CPU generic map(100000000)port map(clk_line,nreset,data_in,regA_out,regB_out,result_out,data_out);

process(regA_out,regB_out,result_out,data_out)
begin
    data_in_A<="00000000"&result_out;
    data_in_B<="00000000"&regB_out;
    data_in_C<="00000000"&regA_out;
    data_in_D<="00000000"&data_out;
end process;

end Behavioral;

顶层:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/25 17:50:57
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CPU is
    generic(
        CLK_FRE:integer:=100000000
    );
    Port(
        clk:in std_logic;
        nreset:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        
        regA_out,regB_out,result_out:out std_logic_vector(7 downto 0);
        data_out:out std_logic_vector(7 downto 0)
    );
end CPU;

architecture Behavioral of CPU is
signal clk1,nclk1:std_logic;   --clk
signal clk2,nclk2:std_logic;   --clk二分频
signal w0,w1,w2,w3:std_logic;   --节拍信号
component clock
    Port(
        clk,rst:in std_logic;
        clk1,nclk1:out std_logic;   --clk
        clk2,nclk2:out std_logic;   --clk二分频
        w0,w1,w2,w3:out std_logic   --节拍信号
    );
end component;

signal clk_uC,M_uA,CMROM_CS:std_logic;
signal IR_line:std_logic_vector(7 downto 0);
signal CTR_BUS:std_logic_vector(47 downto 8);
component uC
    Port(
        clk_uC:in std_logic;    --微程序控制器时钟信号
        nreset:in std_logic;    --复位信号
        M_uA:in std_logic;      --微地址控制信号
        IR:in std_logic_vector(7 downto 2); --IR操作码信息
        CMROM_CS:in std_logic;  --控制存储器选通信号
        
        CM:out std_logic_vector(47 downto 8)    --控制信号输出
    );
end component;

signal clk_SP,SP_CS,SP_UP,SP_DN,nSP_EN:STD_LOGIC;
signal AR:std_logic_vector(6 downto 0);
signal DATA_BUS:std_logic_vector(7 downto 0);
component SP
    Port(
        clk_SP:in std_logic;    --SP时钟信号
        nreset:in std_logic;    --复位信号                
        SP_CS:in std_logic;     --SP选择信号
        SP_UP:in std_logic;     --SP+1控制
        SP_DN:in std_logic;     --SP-1控制
        nSP_EN:in std_logic;    --SP输出使能
        
        AR:out std_logic_vector(6 downto 0);--SP指向RAM地址
        DATA_BUS:inout std_logic_vector(7 downto 0)   --数据总线
    );
end component;

signal clk_IO,IO_CS,IO_IEN,IO_OEN,RI_EN,RO_EN:std_logic;
signal IO_in,IO_out:std_logic_vector(7 downto 0);
component IO
    Port(
        clk_IO:in std_logic;    --IO时钟信号
        nreset:in std_logic;    --IO复位信号
        IO_CS:in std_logic;     --IO选择信号
        IO_IEN:in std_logic;    --IO输入使能
        IO_OEN:in std_logic;    --IO输出使能
        RI_EN:in std_logic;     --IO缓存器输入使能
        RO_EN:in std_logic;     --IO缓存器输出使能
        IO_in:in std_logic_vector(7 downto 0);          --IO输入
        
        IO_out:out std_logic_vector(7 downto 0);        --IO输出
        DATA_BUS:inout std_logic_vector(7 downto 0)    --数据总线
    );
end component;

signal clk_RAM,RAM_CS,nRAM_EN,Wr_nRD:std_logic;
component RAM
    generic(
        depth:positive:=7;
        width:positive:=8
    );
    Port (
        clk_RAM:in STD_LOGIC;       --RAM时钟信号
        n_reset:in STD_LOGIC;       --RAM选择信号
        RAM_CS:in STD_LOGIC;        --RAM片选信号
        nRAM_EN:in STD_LOGIC;       --RAM输出使能
        Wr_nRD :in STD_LOGIC;       --RAM读写信号
        AR:in STD_LOGIC_VECTOR (depth-1 downto 0);  --RAM地址信号
        
        DATA_BUS: inout STD_LOGIC_VECTOR (width-1 downto 0) --数据总线
    );
end component;

signal clk_ALU,m_A,m_B,m_F,nALU_EN,nPSW_EN,C0:std_logic;
signal S :std_logic_vector(4 downto 0);
signal F_in :std_logic_vector(1 downto 0);    
--signal regA_out,regB_out,result_out:std_logic_vector(7 downto 0);
signal AC : std_logic;     --半进位标志
signal CY : std_logic;     --进位标志
signal ZN : std_logic;     --零标志
signal OV : std_logic;      --溢出标志
component ALU 
    port(
        clk,clk_ALU : in std_logic; --全局时钟和ALU时钟
        nreset : in std_logic;      --全局复位信号
        M_A,M_B : in std_logic;     --暂存器控制信号
        M_F : in std_logic;         --程序状态字控制信号
        nALU_EN : in std_logic;     --alu运算结果输出使能
        nPSW_EN : in std_logic;     --psw输出使能
        C0 : in std_logic;          --进位输入
        S : in std_logic_vector(4 downto 0);        --运算类型和操作选择,M为最高位S(4),其余在低四位
        F_in : in std_logic_vector(1 downto 0);     --移位功能选择
        
        regA_out,regB_out,result_out:out std_logic_vector(7 downto 0);
        DATA_BUS : inout std_logic_vector(7 downto 0);  --数据总线
        AC : out std_logic;     --半进位标志
        CY : out std_logic;     --进位标志
        ZN : out std_logic;     --零标志
        OV : out std_logic      --溢出标志
    );
end component;

signal clk_RN,Rn_CS,nRi_EN,RDRi,WRRi:std_logic;
signal RS,RD:std_logic;
component RN
    Port(
        clk_RN,Rn_CS,nRi_EN,RDRi,WRRi:in std_logic;
        RS,RD:in std_logic;

        DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end component;

signal clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen: std_logic;
signal IR_AR       :std_logic_vector(6 downto 0);
component IR
    Port (
        rst,clk_IR,LD_IR1,LD_IR2,LD_IR3,nARen:in std_logic;
        DATA_BUS:in std_logic_vector(7 downto 0);
        
        IR_out:out std_logic_vector(7 downto 0);--传送指令到指令寄存器
        RS,RD:out std_logic;--传送操作寄存器(寄存器地址)
        PC_out:out std_logic_vector(11 downto 0);--PC地址总线
        AR:out std_logic_vector(6 downto 0)
    );
end component;

signal clk_ROM,M_ROM,ROM_EN:std_logic;
signal ROM_PC:std_logic_vector(11 downto 0);
component ROM
    generic(
        depth:positive:=12;
        width:positive:=8
    );
    Port (
        clk_ROM,M_ROM,ROM_EN:in std_logic;
        addr:in std_logic_vector(11 downto 0);
        DATA_BUS:inout std_logic_vector(7 downto 0)
    );
end component;

signal clk_PC,M_PC,nLD_PC,nPCH,nPCL:std_logic;
signal PC_in:std_logic_vector(11 downto 0):=(others=>'0');
component pc
    Port (        
        rst,clk_PC,M_PC,nLD_PC:in std_logic;
        nPCH,nPCL:in std_logic;
        PC_in:in std_logic_vector(11 downto 0);
        
        PC_out:out std_logic_vector(11 downto 0);
        DATA_BUS:inout std_logic_vector(7 downto 0)
     );
end component;

signal test_line:std_logic_vector(7 downto 0);

begin

clock_inst:clock port map(clk,nreset,clk1,nclk1,clk2,nclk2,w0,w1,w2,w3);
PC_inst:PC port map(nreset,clk_PC,M_PC,nLD_PC,nPCH,nPCL,PC_in,ROM_PC,DATA_BUS);
ROM_inst:ROM generic map(12,8)port map(clk_ROM,M_ROM,ROM_EN,ROM_PC,DATA_BUS);
uC_inst:uC port map(clk_uC,nreset,M_uA,IR_line(7 downto 2),CMROM_CS,CTR_BUS);
IR_inst:IR port map(rst=>nreset,clk_IR=>clk_IR,LD_IR1=>LD_IR1,LD_IR2=>LD_IR2,LD_IR3=>LD_IR3,nARen=>nARen,DATA_BUS=>DATA_BUS,IR_out=>IR_line,RS=>RS,RD=>RD,PC_out=>PC_in,AR=>AR(6 downto 0));
RAM_inst:RAM generic map(7,8)port map(clk_RAM=>clk_RAM,n_reset=>nreset,RAM_CS=>RAM_CS,nRAM_EN=>nRAM_EN,Wr_nRD=>Wr_nRD,AR=>AR,DATA_BUS=>DATA_BUS);
IO_inst:IO port map(clk_IO,nreset,IO_CS,IO_IEN,IO_OEN,RI_EN,RO_EN,data_in,data_out,DATA_BUS);
--SP_inst:SP PORT MAP(clk_SP,nreset,SP_CS,SP_UP,SP_DN,nSP_EN,AR,DATA_BUS);
ALU_inst:ALU port map(clk,clk_ALU,nreset,m_A,m_B,m_F,nALU_EN,nPSW_EN,C0,S,F_in,regA_out,regB_out,result_out,DATA_BUS,AC,CY,ZN,OV);
RN_inst:RN port map(clk_RN,Rn_CS,nRi_EN,RDRi,WRRi,RS,RD,DATA_BUS);

clk_PC<=clk1 and clk2;
clk_ROM<=nclk1 and clk2;
clk_IR<=clk1 and nclk2;
clk_uC<=nclk1 and nclk2;
clk_RN<=clk1 and nclk2;
clk_ALU<=nclk1 and nclk2;
--clk_IO<=clk2;--(LED程序使用)
clk_IO<=nclk1 and clk2;--(ADD程序使用)
clk_RAM<=nclk1 and w1;
clk_SP<=clk1 and clk2 and w1;

M_A <= CTR_BUS(47);
M_B <= CTR_BUS(46);
M_F <= CTR_BUS(45);
S(4) <= CTR_BUS(44);
S(3) <= CTR_BUS(43);
S(2) <= CTR_BUS(42);
S(1) <= CTR_BUS(41);
S(0) <= CTR_BUS(40);
F_in(1) <= CTR_BUS(39);
F_in(0) <= CTR_BUS(38);
nALU_EN <= CTR_BUS(37);
nPSW_EN <= CTR_BUS(36);
C0 <= CTR_BUS(35);
RAM_CS <= CTR_BUS(34);
Wr_nRD <= CTR_BUS(33); 
nRAM_EN <= CTR_BUS(32);
Rn_CS <= CTR_BUS(31);
RDRi <= CTR_BUS(30);
WRRi <= CTR_BUS(29);
nRi_EN <= CTR_BUS(28);
LD_IR1 <= CTR_BUS(27);
LD_IR2 <= CTR_BUS(26);
LD_IR3 <= CTR_BUS(25);
nAREN <= CTR_BUS(24);
M_PC <= CTR_BUS(23);
nLD_PC <= CTR_BUS(22); 
nPCH <= CTR_BUS(21); 
nPCL <= CTR_BUS(20); 
SP_UP <= CTR_BUS(19);
SP_DN <= CTR_BUS(18);
SP_CS <= CTR_BUS(17); 
nSP_EN <= CTR_BUS(16); 
IO_CS <= CTR_BUS(15);
IO_IEN <= CTR_BUS(14);
IO_OEN <= CTR_BUS(13);
RI_EN<='0';
RO_EN<='0';
-- <= CTR_BUS(12);
M_ROM <= CTR_BUS(11);
ROM_EN <= CTR_BUS(10);
M_uA <= CTR_BUS(9);
CMROM_CS <= CTR_BUS(8);

process(nPCH,nPCL)
begin
    if(nPCH='0')then PC_in(11 downto 8)<=DATA_BUS(3 downto 0);
    elsif(nPCL='0')then PC_in(7 downto 0)<=DATA_BUS;
    end if;
end process;

end Behavioral;

时钟:

ADD微程序:

00111000 --IR:38H MOV Ri,IO
00111011 --IR:38H MOV Ri,IO
00001000 --ADD R0,R1
00000100 --JMP addr12
00000000 --addr1:00H
00000000 --addr2:00H

LED微程序:

00100100 --IR:24H MOV Ri,#data
00000001 --data:01H
00110100 --IR:34H MOV IO,Ri
00100100 --IR:24H
00000010 --data:02H
00110100 --IR:34H
00100100 --IR:24H
00000100 --data:04H
00110100 --IR:34H
00100100 --IR:24H
00001000 --data:08H
00110100 --IR:34H
00100100 --IR:24H
00010000 --data:10H
00110100 --IR:34H
00100100 --IR:24H
00100000 --data:20H
00110100 --IR:34H
00100100 --IR:24H
01000000 --data:40H
00110100 --IR:34H
00100100 --IR:24H
10000000 --data:80H
00110100 --IR:34H
00000100 --JMP addr12
00000000 --addr:00H
00000000 --addr:00H
00000000

 程序:

000000000011000100011001111100110111100100000000		--00H
000000000000000000000000000000000000000000000000		--01H
000000000000000000000000000000000000000000000000		--02H
000000000000000000000000000000000000000000000000		--03H
000000000011000100010101111100110111101100000101		--04H JMP addr12
000000000011000100010011111100110111101100000110		--05H
000000000011000100010001101100110111011100000000		--06H
000000000000000000000000000000000000000000000000		--07H
010000000011000101000001011100110111011100001001		--08H ADD Ri,Rj
100000000011000101000001011100110111011100001010		--09H
001000010001000100110001011100110111011100000000		--0AH
000000000001000100100001111100110111011100000000		--0BH
000000000000000000000000000000000000000000000000		--0CH
000000000000000000000000000000000000000000000000		--0DH
000000000000000000000000000000000000000000000000		--0EH
000000000000000000000000000000000000000000000000		--0FH
000000000000000000000000000000000000000000000000		--10H
000000000000000000000000000000000000000000000000		--11H
000000000000000000000000000000000000000000000000		--12H
000000000000000000000000000000000000000000000000		--13H
000000000000000000000000000000000000000000000000		--14H
000000000000000000000000000000000000000000000000		--15H
000000000000000000000000000000000000000000000000		--16H
000000000000000000000000000000000000000000000000		--17H
000000000000000000000000000000000000000000000000		--18H
000000000000000000000000000000000000000000000000		--19H
000000000000000000000000000000000000000000000000		--1AH
000000000000000000000000000000000000000000000000		--1BH
000000000000000000000000000000000000000000000000		--1CH
000000000000000000000000000000000000000000000000		--1DH
000000000000000000000000000000000000000000000000		--1EH
000000000000000000000000000000000000000000000000		--1FH
000000000000000000000000000000000000000000000000		--20H
000000000000000000000000000000000000000000000000		--21H
000000000000000000000000000000000000000000000000		--22H
000000000000000000000000000000000000000000000000		--23H
000000000011000100100001111100110111101100100101		--24H MOV Ri,#data ***修改***
000000000011000100010001011100110111011100100110		--25H
000000000011000100010001011100110111011100000000		--26H
000000000000000000000000000000000000000000000000		--27H
000000000011000101100001011100110111011100101001		--28H
000000000011000101100001011100110111011100101010		--29H
000000000011000100010001011100110111011100000000		--2AH
000000000000000000000000000000000000000000000000		--2BH
000000000011000100010010111100110111101100101101		--2CH
000000000011010000100000011100110111011100101110		--2DH
000000000011000100010001011100110111011100000000		--2EH
000000000000000000000000000000000000000000000000		--2FH
000000000011000100010010111100110111101100110001		--30H
000000000011011101000000011100110111011100110010		--31H
000000000011000100010001011100110111011100000000		--32H
000000000000000000000000000000000000000000000000		--33H
000000000011000101000001011100111101011100110101		--34H MOV IO,Ri
000000000011000100010001011100110101011100110110		--35H 
000000000011000100010001011100110111011100000000		--36H
000000000000000000000000000000000000000000000000		--37H
000000000011000100010001011100111011011100111001		--38H MOV Ri,IO
000000000011000100100001011100111001011100111010		--39H
000000000011000100010001011100110111011100000000		--3AH
000000000000000000000000000000000000000000000000		--3BH
000000000011000100010001111100010111101100111101		--3CH
000000000011000100010001011100110111011100111110		--3DH
000000000011000100010001011100110111011100000000		--3EH
000000000000000000000000000000000000000000000000		--3FH
010000010011000101000001011100110111011101000001		--40H
000000000011000101100001011100110111011101000010		--41H
100000000011000111000001011100110111011101000011		--42H
001000010001000100110001111100110111011101000100		--43H
000000000011000100010001011100110111011100000000		--44H
000000000000000000000000000000000000000000000000		--45H

testbench:

----------------------------------------------------------------------------------
-- Engineer: switch_swq
-- Create Date: 2024/04/26 08:47:54
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CPU_tb is

end CPU_tb;

architecture Behavioral of CPU_tb is
component CPU
    generic(
        CLK_FRE:integer:=100000000
    );
    Port(
        clk:in std_logic;
        nreset:in std_logic;
        data_in:in std_logic_vector(7 downto 0);
        
        data_out:out std_logic_vector(7 downto 0)
    );
end component;

signal clk,nreset:std_logic;
signal data_in,data_out:std_logic_vector(7 downto 0);

begin

CPU_inst:CPU generic map(100000000)port map(clk,nreset,data_in,data_out);

clock:process
begin
    clk<='1';
    wait for 5ns;
    clk<='0';
    wait for 5ns;
end process;

reset:process
begin
    nreset<='0';
    wait for 15ns;
    nreset<='1';
    wait;
end process;

test:process
begin
    data_in<=x"FF";
    wait;
end process;

end Behavioral;

LED结果:

整体:

取数(00100100 --IR:24H MOV Ri,#data 00000001 --data:01H): 

IO输出(00110100 --IR:34H MOV IO,Ri): 

ADD结果:

整体:

IO输入(00111000 --IR:38H MOV Ri,IO): 

加法(00001000 --ADD R0,R1): 

xdc:

#CLK_100M
set_property PACKAGE_PIN E10        [get_ports clk]
set_property IOSTANDARD LVCMOS18    [get_ports clk]

#sw31~24
set_property PACKAGE_PIN J8         [get_ports nreset]
set_property IOSTANDARD LVCMOS18    [get_ports nreset]

#SW0~7
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[0]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[1]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[2]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[3]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[4]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[5]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[6]}]
set_property IOSTANDARD LVCMOS18    [get_ports {data_in[7]}]
set_property PACKAGE_PIN C9         [get_ports {data_in[0]}]
set_property PACKAGE_PIN B9         [get_ports {data_in[1]}]
set_property PACKAGE_PIN G11        [get_ports {data_in[2]}]
set_property PACKAGE_PIN F10        [get_ports {data_in[3]}]
set_property PACKAGE_PIN D10        [get_ports {data_in[4]}]
set_property PACKAGE_PIN E11        [get_ports {data_in[5]}]
set_property PACKAGE_PIN D11        [get_ports {data_in[6]}]
set_property PACKAGE_PIN A14        [get_ports {data_in[7]}]

#SEG_DIG1~16
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[15]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[14]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[13]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[12]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[11]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[10]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[9]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[8]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_dig[0]}]
set_property PACKAGE_PIN A23        [get_ports {seg_dig[15]}]
set_property PACKAGE_PIN A24        [get_ports {seg_dig[14]}]
set_property PACKAGE_PIN D26        [get_ports {seg_dig[13]}]
set_property PACKAGE_PIN C26        [get_ports {seg_dig[12]}]
set_property PACKAGE_PIN A20        [get_ports {seg_dig[11]}]
set_property PACKAGE_PIN J25        [get_ports {seg_dig[10]}]
set_property PACKAGE_PIN J24        [get_ports {seg_dig[9]}]
set_property PACKAGE_PIN H22        [get_ports {seg_dig[8]}]
set_property PACKAGE_PIN K21        [get_ports {seg_dig[7]}]
set_property PACKAGE_PIN L23        [get_ports {seg_dig[6]}]
set_property PACKAGE_PIN B25        [get_ports {seg_dig[5]}]
set_property PACKAGE_PIN B26        [get_ports {seg_dig[4]}]
set_property PACKAGE_PIN C24        [get_ports {seg_dig[3]}]
set_property PACKAGE_PIN D21        [get_ports {seg_dig[2]}]
set_property PACKAGE_PIN C22        [get_ports {seg_dig[1]}]
set_property PACKAGE_PIN B20        [get_ports {seg_dig[0]}]

#seg_data
set_property PACKAGE_PIN E26        [get_ports {seg_data[7]}]
set_property PACKAGE_PIN J26        [get_ports {seg_data[6]}]
set_property PACKAGE_PIN H26        [get_ports {seg_data[5]}]
set_property PACKAGE_PIN H21        [get_ports {seg_data[4]}]
set_property PACKAGE_PIN G21        [get_ports {seg_data[3]}]
set_property PACKAGE_PIN H23        [get_ports {seg_data[2]}]
set_property PACKAGE_PIN H24        [get_ports {seg_data[1]}]
set_property PACKAGE_PIN J21        [get_ports {seg_data[0]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[7]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[6]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[5]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[4]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[3]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[2]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[1]}]
set_property IOSTANDARD LVCMOS33    [get_ports {seg_data[0]}]

1.实验结果分析

<1>模块工作顺序分析

        各个模块工作的逻辑顺序如上时钟时序图所示,每条指令执行则可分为m0~3四个阶段。在m0阶段首先由PC发送地址至ROM,然后ROM输出该地址的指令或数据,传送至IR,IR经过简单处理后继续传送至UC,UC产生各个模块的控制信号。在m1~3阶段,依据微程序产生3次控制信号,实现相应指令功能(注意ALU、RN、IO时钟不同,后面有相关解释)。

<2>​​​指令执行过程分析
  • 以ADD加法为例:

MOV Ri,IO:

        m1~3——执行38H MOV Ri,IO:在m1使能IO相关信号使IO_IN->REG,在m2时,REG->DATA_BUS->Ri(IO的时钟先于RN,使数据在DATA_BUS刚好能传送至RN)

ADD R0,R1:

        m1~3——执行08H ADD R0,R1:由于无法在计算出结果的同时将结果通过数据总线DATA_BUS传送至RN,所以在一条指令中,我的ADD指令只能实现计算功能,计算结果由ALU另行输出至result总线。在m1和m2分别实现RN->DATA_BUS->regA/B(其中regA/B为ALU内部缓冲器),在m3实现计算和UC地址回到00H操作。

以LED流水灯为例:

        m0——取指令:PC->ROM->DATA_BUS->IR->UC,微指令为0x003119f37900H

        注意到ROM将地址信息输出到总线,IR接收并传递地址到UC,从而执行24H地址的微程序。

MOV Ri,#data:

        m1~3——执行24H MOV Ri,#data:在m1将ROM中的立即数输出至

DATA_BUS,在m2传输至Ri之中,在m3阶段UC地址回到00H准备进入下一条指令,即取值公操作。

MOV IO,Ri:

        m1~3——执行34H MOV IO,Ri:在m1将Ri->DATA_BUS,在m2,DATA_BUS->REG->IO_OUT(REG是IO内暂存器,由于UC控制信号不包含RI_EN和RO_EN,一直使能,即DATA_BUS<->IO直接完成),在m3阶段UC地址回到00H准备进入下一条指令,即取值公操作。

JMP addr12

        m1~3——执行04H JMP addr12:在m1、m2依次将立即数加载至IR中,对应LD_IR2和LD_IR3分别有效,IR将新地址传送至PC。

  • 以ADD加法为例:

MOV Ri,IO:

        m1~3——执行38H MOV Ri,IO:在m1使能IO相关信号使IO_IN->REG,在m2时,REG->DATA_BUS->Ri(IO的时钟先于RN,使数据在DATA_BUS刚好能传送至RN)

ADD R0,R1:

        m1~3——执行08H ADD R0,R1:由于无法在计算出结果的同时将结果通过数据总线DATA_BUS传送至RN,所以在一条指令中,我的ADD指令只能实现计算功能,计算结果由ALU另行输出至result总线。在m1和m2分别实现RN->DATA_BUS->regA/B(其中regA/B为ALU内部缓冲器),在m3实现计算和UC地址回到00H操作。

2.其他

<1>SOC模块集成设计经验

        在集成各个组成模块时,为避免总线冲突以及方便调试,采用各个模块依次添加测试的方法。

        首先测试PC、ROM、IR、UC组成的系统,要求取指令时4个模块的运行顺序为:PC发送ROM地址->ROM输出指令/数据->IR传送指令->UC解析执行微程序。随后依次加入IO、RN、ALU、RAM模块进行调试(按照指令执行逻辑顺序)。

<2>SOC集成关键

在集成各个模块时,关键在于:

  • 清楚模块工作逻辑顺序

        需清楚知晓各个模块工作先后关系,理清数据/控制/地址信号流的传递顺序,以避免读写顺序出错,出现写未读到的情况。

  • 避免总线冲突

        主要是DATA_BUS数据总线使用的原子性,各模块严格按照时钟时序进行输出,在允许输出时输入/出数据到数据总线,其他时刻不要忘记将数据总线置高阻态。

  • 考虑信号的建立、保持

        在课程参考资料中,ALU、IO、RN的时钟都是nclk2,但是对于任意一条微指令,如果涉及到上述3个模块的协作,如将RN中数据传送至ALU中缓存器regA,由于时钟相同,且都在上升沿工作,则在同一时刻,RN中数据传输到数据总线,上一时刻数据总线的数值传送至regA,并不能实现RN->DATA_BUS->regA这一连贯操作。

        解决方法在于错开操作时间,即RN->DATA_BUS先于DATA_BUS->regA,需要修改模块时钟,故出现了上面仿真图中的时钟。

<3>反思与改进

  • 对数据不能在总线上连续传递的思考

        考虑上面“考虑信号的建立、保持”部分产生的问题,问题产生的原因在于组合逻辑电路和时序逻辑电路的区别,如果将信号的触发条件由时钟的上升沿改为高电平(类似于使能信号),则将时序逻辑转变为组合逻辑,可能解决上述问题,使得ALU、IO、RN等模块的时钟可以都是nclk2。

  • ADD指令的改进

        上述实现的ADD指令在有限的m1~3阶段内计算完结果无法实现结果存储至RN(在上面ADD指令时序图可观测到计算结果曾短时间内输出到数据总线DATA_BUS上),仅一个指令周期无法实现,可以扩展成两个,即在第二个指令周期的m0~3阶段实现指令存储至RN。

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