FPGA学习笔记（二）——模块的例化

• 模块的例化
  设计模块

module uart(
	clk,
	rst_n,
	vld_in,
	data_in,
	uart_out,
	uart_in,
	vld_out,
	data_out,
	rdy_in
);

例化模块

uart u_uart(
	.clk	(clk_100m),
	rst_n	(sys_rst_n),
	vld_in	(bt_data_out_vld),
	data_in	(ba_data_out),
	uart_out	(uart_tx),
	uart_in	(uart_rx),
	vld_out	(uart_data_out_vld),
	data_out	(uart_data_out),
	rdy_in	(uart_in_rdy)
);

设计模块名 例化模块名（
	.设计模块信号（例化模块信号）
）;

• 参数例化

module uart(
	clk,
	rst_n,
	vld_in,
	data_in,
	uart_out,
	uart_in,
	vld_out,
	data_out,
	rdy_in
);

parameter DATA_W = 8;

uart#(.DATA_W(16)) u_uart(
	.clk	(clk_100m),
	rst_n	(sys_rst_n),
	vld_in	(bt_data_out_vld),
	data_in	(ba_data_out),
	uart_out	(uart_tx),
	uart_in	(uart_rx),
	vld_out	(uart_data_out_vld),
	data_out	(uart_data_out),
	rdy_in	(uart_in_rdy)
);