Formal Evaluation

Definition

Formal verification (形式验证) ： 根据某个或某些形式规范，利用数学的方法证明其正确性或非正确性；
(Formal verification methods make use of mathematical techniques to insure the integrity of a design with respect to some desired characteristics)

Metrics For Approximate Computing

• Worst Case Error:
  
• Worst-Case-Relative Error
  
• Average-Case Error
  
• Average-Case-Relative Error
  
• The Mean-Squared Error
  
• Error Rate
  
• Bit-Flip Error
  

Method

Exact Circuit: equivalence checking;
AC: relaxed equivalence checking.

SAT/BDD

Algorithm for computing Worst case absolute error by using Miter (b):

This can be seen as the binary-search version LEXSAT.
=> For different metrics，using different error computing circuits:

Challenge:

The computational complexity dramatically increases with a decreasing error, especially on multipliers. Unfortunately, the multiplier is one of the key arithmetic circuits that is widely used in many applications, especially in digital signal processing and multimedia processing. Hence, there is currently a clear need to come up with a more powerful approach to the problem of evaluating the quality of complex approximate digital circuits. A combination of the circuit simulator and a SAT-solver seems to be a promising approach which helps us to further improve the performance of the analysis.[1]

[1] Z. Vasicek, “Formal methods for exact analysis of approximate circuits,” IEEE Access, vol. 7, no. 1, pp. 177 309–177 331, 2019.