本文详细介绍了ETM（Extracted Timing Model）模型中关于面积、漏电流、时序类型、接口时序、宏单元标识和块距离等关键参数的含义。同时，针对输入和输出引脚的参数，如电容、最大转换、时序类型、最小周期、脉冲宽度等进行了解析。此外，还讨论了输入到寄存器路径、寄存器到输出路径和输入到输出路径的时序建模方式。最后，提到了如何理解和验证ETM中的功率数值。
| ETM snippet | Reported parameters | Explanation | |
| cell (block) { | area | The tool writes out the area in an ETM as the sum of the areas of all instances present in the block, as is defined in the timing library. | |
| cell_leakage_power | Leakage power is implemented at the cell level in an ETM and is equal to the leakage power seen during block STA. This will be dumped when you use the -include_power option with do_extract_model and set the timing_library_read_without_power global as false before reading the timing libraries. For more details, refer to the following article: | ||
| timing_model_type | This represents the model type for a given cell. This will always be 'extracted' for an ETM. | ||
| interface_timing | Here, a true value represents that the library cell has an interface timing specified for that cell. | ||
| is_macro_cell | The model extractor always writes "is_macro_cell : true" in the ETM to identify the cell as a macro. | ||
| block_distance | This is the diagonal distance of the block for which the ETM is being generated. This attribute is written in an ETM by default and is used while applying Spatial timing derates at the top level. | ||
Input pin (Data) Parameters:
| ETM snippet | Reported parameters | Explanation | |
| pin (d ) { | capacitance | This is the capacitance of the connected net and all fanout/fan-in pins. You can use the following command to get a detailed information: | |
| timing_type | timing_type : setup_rising / hold_rising arc The tool writes out these arcs for In2Reg paths, which are valid constrained timing paths. If the resulting ETM does not have hold constraints (hold_rising/hold_falling), it means that for early analysis, this path is unconstrained. You can check this by using: | ||
Input pin (Clock) Parameters:
| ETM snippet | Reported parameters | Explanation | |
| pin (ck ) {
| direction | input: If a clock is created on a design port, this port will be preserved as an ETM I/O pin with the same name as that of the port itself. internal: If create_clock is applied on a pin of the design (not port) or generated clock defined in a block, such pin is modeled as an internal pin and by default, the name of the internal pin will be same as that of the clock. For a generated clock, the timing_extract_model_preserve_clock_name_as_internal_pin true variable preserves the generated clock source pin name in the extracted model. This variable will be honored only for the generated clocks created on the block pin, not create_clock. | |
| min_period | Period constraints defined at the CK pin of the registers are transferred to the clock source pins during the model extraction. If there are multiple registers at the fanout of a clock source, the minimum period at the clock source will be picked from the worst minimum-period value out of all fanout registers. | ||
| min_pulse_width_* | MPW defined at the CK pin of the registers are transferred to the clock source pin in the ETM. These checks can be modeled in the following three ways:
To understand the calculation of this value, refer to the following article: "How is MPW modeled in ETM?". | ||
| internal_power() { | The internal power is modeled for the entire block on one port and is written when the -include_power option is used with do_extract_model and the timing_library_read_without_power global is set to false before reading timing libraries. | ||
| timing_type | min_clock_tree_path / max_clock_tree_path : The do_extract_model command will write out this by setting the following global to true: | ||
Output pin parameters:
| ETM snippet | Reported parameters | Explanation | |
| pin (q ) { direction : output ; capacitance : 0.0000; max_transition : 4.5000; max_capacitance : 0.3115; is_isolated : true; always_on : true; function : "0" ; timing() { timing_type : rising_edge ; timing_sense : non_unate ; min_delay_arc : "true" ; related_pin :" ck "; rise_transition (lut_timing_1 ){ |
| ETM models DRVs on pins by worst-casing the DRV specified using the following methods:
The following switch is used to consider the DRV applied on the design: | |
| is_isloated | This attribute comes when -pg option is used with do_extract_model command and input has upf/cpf. This construct is getting written in ETM for pins which have driver/load cell defined as isolation cell. (timing library will have attribute is_isolation_cell true for such cells). | ||
| always_on | This attribute comes when -pg option is used with do_extract_model command. This construct is getting written in ETM for pins which have driver/load pin defined as always_on true. (timing library will have attribute always_on true for such cells). > get_property [get_property [get_nets [get_property [get_ports <port_name>] net_name]] driver_pins] is_always_on | ||
| function : "0" ; | ETM models the constant as a function in the library if these propagate to the output port. However, if you do not want to write out the propagated constant, you can set the following global variable to false: set_global timing_extract_model_case_analysis_in_library false If you set this global to false, then the constants propagated to the output port through set_case_analysis will be written in the constraints file (*.asrt) as shown here: set_case_analysis 0 q Note: "function : 0" or "function : 1" will be modeled for Verilog and library constants irrespective of the state of the timing_extract_model_case_analysis_in_library global. Only user-defined case analysis modeling (set_case_analysis) will be impacted by this global. | ||
| timing_type | rising_edge / falling_edge : combinational_rise / combinational_fall : | ||
| min_delay_arc | In the extracted model for combinational/trigger/latency arc (such as q -> ck ), both the rise/fall maximum and minimum arcs exist. This early/late attribute is differentiated through the min_delay_arc attribute. The tool does not honor this in the analysis. For example, if for some reason during ETM modeling, the late combinational delay is smaller than the early combinational delay, the tool would still use larger delays for late analysis (which were modeled inside min_delay_arc) and smaller delays for early analysis with ETM. | ||
Input to Register Paths
Input to register paths are the paths from an input port to a register. In an ETM, the input to register
paths are represented by equivalent setup or hold checks. These checks contain the calculated
delay from the input port to the register, the setup or hold value of the library cell and the delay from a
clock source to the clock pin of the register. The delay for the setup or hold checks is the function of
the transition on the input port and the transition at the clock source
Setup check delay = delay (input to register) + delay (setup value of register) - delay (clock source to
clock pin)
Hold check delay = delay (input to register) - delay (hold value of register) - delay (clock source to
clock pin)
If multiple clocks reach a register, then the software extracts separate setup or hold arc for each clock
source.
Register to Output Paths
The register to output paths are the path from a register to an output port. These paths are a
combination of a trigger arc of starting register and the combinational delay from sink of trigger arc to
the output port. Therefore the software extracts an equivalent trigger or sequential arc for register to
output paths.
The delay for these arcs is a function of the slew at the clock source and the capacitance at the
output port. The delay of the arc is calculated as follows:
Sequential arc delay = delay (clock source to clock pin of register) + delay (register clock pin to out
port)
The software generates two arcs representing longest and shortest path because the generated
ETM can be used for both max and min analysis. The software generates different types of arcs for
different valid clock edges such as rising_edge or falling_edge.
Input to Output Paths
The input to output paths are the paths from an input port to an output port. These are combinational
paths. Therefore the software generates equivalent combinational arc for these paths.
The delay for these arcs is a function of the slew at the input port and the capacitance at the output
April 2014 360 Product Version 14.1
Tempus User Guide
Extracting Timing Models
port. The delay for the arc is calculated as follows:
Combinational arc delay = delay (delay of all elements in the path)
The software generates two combinational arcs representing longest and shortest path because the
generated ETM can be used for both max and min analysis. In case a path does not exist for a
particular transition (rise or fall), the software generates half unate arcs such as combinational_rise
or combinational_fall. The timing sense for the arc depends on the function of worst (early or late)
paths.
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