verilog仿真输出信号值到文件中

如：

`timescale 1ns/1ns

module shift_tb;

reg clk, rst;
reg [31:0] count = 32'd0;
wire k1, k2, k3, k4, k5, z;

initial begin
   file = $fopen("D:/data_o.csv","w");  // 初始化文件
end

initial begin
    clk = 0;
    rst = 1;
    #1000 rst = 0;
end

always #10 clk = ~clk;

always @(posedge clk) begin
    if (count < 16'd1000) begin
         $fwrite(file,"%b\n", k1);  //k1为需要保存的信号数据
         count <= count + 1;
     end
     else begin
         count <= 16‘d0;
         $fclose(file);   // 这里一定要写，关闭文件读写
     end
 end

shift u0(
    .clk(clk),
    .rst(rst),
    .k1(k1),
    .k2(k2),
    .k3(k3),
    .k4(k4),
    .k5(k5),
    .z(z)
    );

endmodule