数据包文格式分为数据包文和控制包文格式
//第一段
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
state_c<=HEAD;
end
else begin
state_c<=state_n;
end
end
//第二段
always @(*)begin
case(state_c)
HEAD:begin
if (head_cnt==9&&din==0'hd5)
state_c=TYPE;
else begin
state_c=HEAD;
end
end
TYPE:begin
if (din==0) begin
state_c=DATA;
end
else begin
state_c=LEN;
end
end
LEN:begin
if (len_cnt==1) begin
state_c=DATA;
end
else begin
state_c=LEN;
end
end
DATA:begin
if (data_cnt==0) begin
state_c=FCS;
end
else begin
state_c=DATA;
end
end
FCS:begin
if (fcs_cnt==3) begin
state_c=HEAD;
end
else begin
state_c=FCS;
end
end
endcase
end
第三段多个输出设计
辅助HEAD 中间变量
//head_cnt
//head_cnt
reg [3:0] head_cnt;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
head_cnt<=0;
end
else if(state_c==HEAD)begin
if (head_flag==0)begin//检测55
if (din==8'h55) begin
head_cnt<=head_cnt+1;
end
else begin
head_cnt<=0;
end
end
else if(head_flag==1)begin
if (din==8'hd5)begin
if (head_cnt==9)begin
head_cnt<=0;
end
else begin
head_cnt<=head_cnt+1;
end
end
else if(din==8'h55)begin
head_cnt<=1;
end
else begin
head_cnt<=0;
end
end
else begin
head_cnt<=0;
end
end
else begin
head_cnt<=0;
end
end
head_flag
head_flag=0,等待55
head_flag=1,等待d5
//head_flag
reg head_flag;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
head_flag<=0;
end
else if (state_c==HAED)begin
if(din==8'h55)begin
head_flag<=1;
end
else begin
head_flag<=0;
end
end
else begin
head_flag<=0;
end
end
辅助LEN,中间变量
len_cnt
//len_cnt
reg len_cnt;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
len_cnt<=0;
end
else if(state_c==LEN)begin
len_cnt<=len_cnt+1;
end
else begin
len_cnt<=0;
end
end
辅助DATA 中间变量
data_cnt
//data_cnt
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
data_cnt<=0;
end
else if(state_c==TYPE&&din==0 )begin
data_cnt<=64-1;
end
else if(state_c==LEN)begin
if(len_cnt==0)begin
data_cnt<={data_cnt[7:0],din};
end
else begin
data_cnt<={data_cnt[7:0],din}-1;
end
end
else if(data_cnt!=0)begin
data_cnt<=data_cnt-1;
end
end
辅助FCS 中间变量
fcs_cnt
//fcs_cnt
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
fcs_cnt<=0;
end
else if(state_c==FCS)begin
if(fcs_cnt==3)begin
fcs_cnt<=0;
end
else begin
fcs_cnt<=fcs_cnt+1;
end
end
else begin
fcs_cnt<=0;
end
en
信号 输出
//dout
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout<=0;
end
else begin
dout<=din;
end
end
//dout_vld
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout_vld<=0;
end
else if (state_c!=HEAD)begin
dout_vld<=1;
end
else begin
dout_vld<=0;
end
end
//dout_sop
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout_sop<=0;
end
else if(state_c==TYPE) begin
dout_sop<=1;
end
else begin
dout_sop<=0;
end
end
//dout_eop
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout_eop<=0;
end
else if(state_c==FCS&&fcs_cnt==3) begin
dout_eop<=1;
end
else begin
dout_eop<=0;
end
end