`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [119:0] data_lock ; //5*24
reg [3:0] valid_cnt ;
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
valid_cnt <= 'd0;
else if(valid_in)begin
if(valid_cnt == 4'd15)
valid_cnt <= 4'd0;
else
valid_cnt <= valid_cnt + 1'd1;
end
end
always @(posedge clk or negedge rst_n ) begin
if(!rst_n) begin
data_lock <= 'd0;
data_out <= 'd0;
end
else if(valid_in)begin
if(valid_cnt == 4'd5)begin
data_lock <= {data_lock[119:16], data_in[15:0]};
data_out <= {data_lock, data_in[23:16]};
end
if(valid_cnt == 4'd10)begin
data_lock <= {data_lock[119:8], data_in[7:0]};
data_out <= {data_lock[111:0], data_in[23:8]};
end
if(valid_cnt == 4'd15)begin
data_lock <= {data_lock[119:24], data_in};
data_out <= {data_lock[103:0], data_in};
end
else
data_lock <= {data_lock[95:0], data_in};
end
end
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
valid_out <= 'd0;
else if(valid_in && valid_cnt == 4'd5)begin
if(valid_cnt == 4'd5)
valid_out <= 1'd1;
else if(valid_cnt == 4'd10)
valid_out <= 1'd1;
else if(valid_cnt == 4'd15)
valid_out <= 1'd1;
end else begin
valid_out <= 'd0;
end
end
endmodule