24位数据转128位

实现24bit数据输入转换为128bit数据输出。其中，先到的数据应置于输出的高bit位。电路的接口如下图所示。valid_in用来指示数据输入data_in的有效性，valid_out用来指示数据输出data_out的有效性；clk是时钟信号；rst_n是异步复位信号。

此题关键在于将24位数据凑成128Bit
因为128 * 3 = 24 * 16

直接给出代码：

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    reg [3:0]   cnt;
    reg [127:0] data_lock;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 0;
        else
            cnt <= ~valid_in? cnt:cnt+1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            valid_out <= 0;
        else
            valid_out <= (cnt==5 || cnt==10 || cnt==15)&&valid_in;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_lock <= 0;
        else
            data_lock <= valid_in? {data_lock[103:0], data_in}: data_lock;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_out <= 0;
        else if(cnt==5)
            data_out <= valid_in? {data_lock[119:0], data_in[23:16]}: data_out;
        else if(cnt==10)
            data_out <= valid_in? {data_lock[111:0], data_in[23: 8]}: data_out;
        else if(cnt==15)
            data_out <= valid_in? {data_lock[103:0], data_in[23: 0]}: data_out;
        else
            data_out <= data_out;
    end
endmodule

`timescale 1ns/1ns
module tb();
    reg clk;
    reg rst_n;
    reg valid_in;
    reg [23:0]data_in;

    wire [127:0]data_out;
    wire valid_out;

    width_24to128 dut (
                        .clk(clk),
                        .rst_n(rst_n),
                        .valid_in(valid_in),
                        .data_in(data_in),
                        .data_out(data_out),
                        .valid_out(valid_out)
                      );

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        rst_n = 0;
        #15 rst_n = 1;
    end

    initial begin
        valid_in = 0;
        #15 valid_in = 1;
    end
    initial begin
        data_in = 0;
        #15 data_in = $urandom;
        #10 data_in = $urandom;
        #10 data_in = $urandom;
        #10 data_in = $urandom;
        #10 data_in = $urandom;
        #10 data_in = $urandom;
        #200 $stop;
    end
    endmodule

仿真波形如下：