1 程序代码
module remote_rcv(
input sys_clk , //系统时钟
input sys_rst_n , //系统复位信号,低电平有效
input PULSE // 输入脉冲
);
reg r0;
reg r1;
reg pos_remote_in;
reg neg_remote_in;
assign pos_remote_in = (~r1) & r0;//上升沿
assign neg_remote_in = r1 & (~r0);//下降沿
always @(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n) begin
r0 <= 1'b0;
r1 <= 1'b0;
end
else begin
r0 <= PULSE;
r1 <= r0;
end
end
endmodule