Verilog实现组合8-bit组合逻辑乘法器

module mult8(
    input   wire    [7:0]   a,b,
    
    output  reg     [15:0]  y
    );

reg [7:0] b0,b1,b2,b3,b4,b5,b6,b7;
reg [15:0] y0,y1,y2,y3,y4,y5,y6,y7;

always@(*)  begin
    b0 = {8{b[0]}};
    b1 = {8{b[1]}};
    b2 = {8{b[2]}};
    b3 = {8{b[3]}};
    b4 = {8{b[4]}};
    b5 = {8{b[5]}};
    b6 = {8{b[6]}};
    b7 = {8{b[7]}};
    
    y0 = {8'b00000000,b0&a};
    y1 = {7'b0000000,b1&a,1'b0};
    y2 = {6'b000000,b2&a,2'b00};
    y3 = {5'b00000,b3&a,3'b000};
    y4 = {4'b0000,b4&a,4'b0000};
    y5 = {3'b000,b5&a,5'b00000};
    y6 = {2'b00,b6&a,6'b000000};
    y7 = {1'b0,b7&a,7'b0000000};
    
    y = ((y0 + y1) + (y2 + y3)) + ((y4 + y5) + (y6 + y7));
end

endmodule

module tb_mult8();
reg  [7:0]   a,b;
wire [15:0]  y;

initial begin
    a = 0;
    b = 0;
    #30 a = 4;
    #30 b = 4;
end

mult8   mult8_inst
(
    .a( a ),
    .b( b ),
 
    .y( y )
);

endmodule