Verilog实现任意位宽同步FIFO

主模块：

module syn_FIFO#(
    parameter   DEPTH = 3, //2^DEPTH等于RAM深度
                WIDTH = 8  //数据位宽
)(
    input   wire                clk, rst_n,
    input   wire                wr_en, rd_en,
    input   wire    [WIDTH-1:0] wr_data,
    
    output  wire                full, empty,
    output  reg     [WIDTH-1:0] rd_data
    );
    
reg [WIDTH-1:0] FIFO_mem[0:2**DEPTH-1];  //定义FIFO内部存储空间

wire [DEPTH-1:0]  wr_addr, rd_addr;  //读写地址
reg  [DEPTH:0]    wr_addr_ptr, rd_addr_ptr;  //读写地址指针,用来判断FIFO的空满

assign  wr_addr = wr_addr_ptr[DEPTH-1:0];
assign  rd_addr = rd_addr_ptr[DEPTH-1:0];

always@(posedge clk or negedge  rst_n)
    if(!rst_n)
        wr_addr_ptr <= 0;
    else    if(wr_en && !full)
        wr_addr_ptr <= wr_addr_ptr + 1;
    else
        wr_addr_ptr <= wr_addr_ptr;


always@(posedge clk or negedge  rst_n)
    if(!rst_n)
        rd_addr_ptr <= 0;
    else    if(rd_