Verilog实现4-bit行波进位加法器和超前进位加法器

最新推荐文章于 2024-05-06 17:32:09 发布

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最新推荐文章于 2024-05-06 17:32:09 发布

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分类专栏：数字芯片文章标签： verilog fpga

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1. 行波进位实现方式：

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1. 行波进位实现方式：

module adder4_ripple
(
    input   wire    [3:0] a, b,
    input   wire    Cin0,
    
    output  wire    [3:0] y,
    output  wire    Cout
);

wire  Cin1, Cin2, Cin3;
    
full_adder1 a1(a[0], b[0], Cin0, y[0], Cin1);
full_adder1 a2(a[1], b[1], Cin1, y[1], Cin2);
full_adder1 a3(a[2], b[2], Cin2, y[2], Cin3);
full_adder1 a4(a[3], b[3], Cin3, y[3], Cout);

endmodule


module full_adder1
(
    input   wire   a, b,
    input   wire   Cin,
    
    output  wire   y, Cout
);

assign  y = a ^ b ^ Cin;
assign  Cout = (a & b) + (a & Cin) + (b & Cin);

endmodule

module tb_adder4();
reg [3:0] a,b;
reg Cin0;

wire [3:0] y;
wire Cout;

initial begin
    a = 4'd5;
    Cin0 = 1'b1;
    b = 4'd8;
    #50 a = 4'd1;
    #50 a = 4'd3;
    #50 b = 4'd7;
    #50 a = 4'd10;
end

adder4_ripple ad