CPU设计之取值模块设计

module IF(
    input clk,
    input nrst,
    input stall,
    input br_en,
    input [31:0 ] br_addr,
    output [31:0] PC,
    output [31:0] ins_out
    );
    
    reg CEN = 1'b0;
    reg WEN = 1'b1;
    reg BWEN = 32'h0;
    reg [31:0] D = 32'h0;
    
    reg [31:0] PC_reg = 32'h0;
    
    imem imem0(
       .CLK(clk),
       .CEN(CEN),
       .WEN(WEN),
       .BWEN(BWEN),
       .A(PC[9:2]),
       .D(D),
       .Q(ins_out)
    );
    
 
always @ (posedge clk)
begin
    if(~nrst)
        begin
            PC_reg = 32'h0;
        end
    
    else if(~stall)
        PC_reg <= PC + 32'd4;
        
end
 
assign PC = br_en ? br_addr:PC_reg;
 
endmodule

module IF_tb(
 
    );
    
   reg clk;
   reg nrst;
   reg stall;
   reg br_en;
   reg [31:0 ] br_addr;
   wire [31:0] PC;
   wire [31:0] ins_out;
    
    IF IF1 (
        .clk(clk),
        .nrst(nrst),
        .stall(stall),
        .br_en(br_en),
        .br_addr(br_addr),
        .PC(PC),
        .ins_out(ins_out)
    );
 
 
initial
    begin
        clk = 0;
        nrst = 1;
        stall = 0;
        br_en = 0;
        br_addr = 32'h2;
    
        #100 stall = 1;
        
        #100 stall = 0;
        
        #50 br_en = 1;
        #50 br_en = 0;
    
    
    end
    
  
    
always #5 clk = ~clk;
 
    
endmodule