verilog简单驱动sram

//sram     input 50Mhz    
module sram(
          clk,sw,k,                                 //input
          sram_we_n,sram_oe_n,sram_ce_n,            //output
          sram_ub_n,sram_lb_n,                      //output
          sram_addr,hex,                            //output
          sram_data                                 //inout
);

input clk,k;
input [6:0] sw;
output sram_we_n,sram_oe_n,sram_ub_n,sram_lb_n,sram_ce_n;
output reg [17:0] sram_addr;
output [6:0] hex;
inout [15:0] sram_data;

//一直使能 高低位都不屏蔽 oe读取数据一直拉低  we低写数据 高读数
//写使能和读使能同时拉低 写数据
assign sram_ce_n=1'b0;
assign sram_oe_n=1'b0;
//原来都赋值1 掩码信号低电平有效  以为低电平就掩码 
//经过一番调试 又看了看发现低电平才能读写
assign sram_ub_n=1'b0;
assign sram_lb_n=1'b0;
//--------------------------数据传输-------------------
reg sram_we_n;
assign sram_data=sram_we_n? 16'hzzzz:{9'b0,sw};
//Warning: Output pin "hex[]" driven by bidirectional pin "sram_data[]" cannot be tri-stated
//assign hex=sram_data[6:0];  直接这样不如直接用sram_data就好了
//为了防止误读数据当读有效时 把数据送给数码管
assign hex=sram_we_n?sram_data[6:0]:6'bz;

//--------------------------读写交替----------------------
parameter write=1'b0;
parameter read =1'b1;
reg current_state,next_state;
always@(posedge clk)
begin
    current_state<=next_state;
end

always@(posedge clk)
begin
    case(current_state)
     write: next_state<=read;
     read : next_state<=write;
    endcase
end
//-----一直读取一个地址  可写入两个地址----------------
//当k为0  输出hex随输入sw变化  k=1输出固定
always@(posedge clk)
begin
    case(current_state)
     //write: begin sram_addr<={17'b0,k};sram_we_n<=0; end
     //read : begin sram_addr<=18'b0;    sram_we_n<=1; end
     write: begin sram_addr<=18'b0;      sram_we_n<=0; end
     read : begin sram_addr<={17'b0,k};  sram_we_n<=1; end
    endcase
end

endmodule