verilog 序列检测模块 task用法

检测“1001101010”序列

module xlj(
	input clk,
	input rst_n,
	input signal,
	output reg valid
	);
	
reg [3:0] state;
parameter IDLE = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;
parameter S4 = 4;
parameter S5 = 5;
parameter S6 = 6;
parameter S7 = 7;
parameter S8 = 8;
parameter S9 = 9;
parameter S10 = 10;
always @(posedge clk or negedge rst_n)
	if(~rst_n)begin
		valid <= 0;
		state <= IDLE;
	end
	else
        case(state)
            IDLE:begin
                valid <= 0;
                if(signal)
                    state <= S1;
                else
                    state <= IDLE;
            end
            S1:begin
                if(!signal)
                    state <= S2;
                else
                    state <= S1;
            end
            S2:begin
                if(!signal)
                    state <= S3;
                else
                    state <= S1;
            end
            S3:begin
                if(!signal)
                    state <= IDLE;
                else
                    state <= S4;
            end
            S4:begin
                if(!signal)
                    state <= S2;
                else
                    state <= S5;
            end
            S5:begin
                if(!signal)
                    state <= S6;
                else
                    state <= S1;
            end
            S6:begin
                if(!signal)
                    state <= S3;
                else
                    state <= S7;
            end
            S7:begin
                if(!signal)
                    state <= S8;
                else
                    state <= S1;
            end
            S8:begin
                if(!signal)
                    state <= S3;
                else
                    state <= S9;
            end
            S9:begin
                if(!signal)begin
                    state <= S10;
                    valid <= 1;
                end
                else
                    state <= S1;
            end
            S10:begin
                valid <= 0;
                if(!signal)
                    state <= S3;				
                else
                    state <= S1;
            end
            default:begin
                valid <= 0;
                state <= IDLE;
            end		
        endcase
endmodule 

testbench
使用 task实现激励信号的输入

module tb(

    );
reg clk   ;
reg rst_n ;
reg signal;
wire valid ;
reg en;

initial begin
   clk = 0;
   rst_n = 0;
   signal = 0;
   #100;
   rst_n = 1;
   #20;
   repeat(6)begin
       @(negedge clk);
       signal = {$random}%2;
   end
   series_gen(10'b1001101010);
   repeat(100)begin
       @(negedge clk);
       signal ={$random}%2;
   end
   $finish;
end
always #10 clk=~clk;  

integer i;
task series_gen(input [9:0] series);
    for(i=9;i>=0;i=i-1)begin
        @(negedge clk);
        signal = series[i];
    end
endtask
 
xlj xlj(
	.clk   (clk   ),
	.rst_n (rst_n ),
	.signal(signal),
	.valid (valid )
	);
	
endmodule