verilog 中的task语句使用注意情况

这里我们定义一个任务，并对其进行测试。具体代码如下：

module task_test(
 input sys_clk,
 input rst_n,
 input [31:0]cntA,
 input [31:0]cntB
);

reg  r_pluse_out1;  
reg  r_pluse_out2;  
reg  r_pluse_out3;  
reg  r_pluse_out4;  
    
 always @(*)   begin
 if(!rst_n)begin
 r_pluse_out1<=1'b0;  
 r_pluse_out2<=1'b0;  
 r_pluse_out3<=1'b0;  
 r_pluse_out4<=1'b0;end
 else
 PLUSE_OUT(cntA,cntB,r_pluse_out1,r_pluse_out2,r_pluse_out3,r_pluse_out4);
 end
  
  
  //定义任务  
    task  PLUSE_OUT;
    input [31:0]count;
    input [31:0]R_conut;
    output pluse_out1;
    output pluse_out2;
    output pluse_out3;
    output pluse_out4;    
begin 
    if(count<=R_conut)
     begin
         pluse_out1<=1'b1;
         pluse_out2<=1'b0;
         pluse_out3<=1'b0;
         pluse_out4<=1'b0;
      end
     else if ((count>R_conut)&(count<=R_conut*2))
     begin
         pluse_out1<=1'b0;
         pluse_out2<=1'b1;
         pluse_out3<=1'b0;
         pluse_out4<=1'b0;
      end
    else if ((count>R_conut*2)&(count<=R_conut*3))
     begin
         pluse_out1<=1'b0;
         pluse_out2<=1'b0;
         pluse_out3<=1'b1;
         pluse_out4<=1'b0;
      end
    else if ((count>R_conut*3)&(count<=R_conut*4))
     begin
         pluse_out1<=1'b0;
         pluse_out2<=1'b0;
         pluse_out3<=1'b0;
         pluse_out4<=1'b1;
      end
    else
     begin
        pluse_out1<=1'b0;
        pluse_out2<=1'b0;
        pluse_out3<=1'b0;
        pluse_out4<=1'b0;
     end
 end
 endtask
 
endmodule

代码中定义了任务，实现根据条件依次输出四路脉冲。

testbench如下：

module testbench();
reg sys_clk;
reg rst_n;
reg [31:0]cntA;
reg [31:0]cntB;
 task_test u_task_test(
.sys_clk(sys_clk),
.rst_n(rst_n),
.cntA(cntA),
.cntB(cntB));


initial  sys_clk=10;
always #10 sys_clk=~sys_clk;
    
initial begin
    rst_n=0;
    cntA=0;
    cntB=0;
    #100
    rst_n=1;
    cntB=100;
    #100
   repeat(10000)
   begin
    #20
    cntA=cntA+1;
   end
   #10000
  $stop;
end
      
endmodule

仿真波形如下：

这里出现了不定态，

返回修改代码，将task 定义中的"<="改成“=”再仿真

 task  PLUSE_OUT;
    input [31:0]count;
    input [31:0]R_conut;
    output pluse_out1;
    output pluse_out2;
    output pluse_out3;
    output pluse_out4;    
begin 
    if(count<=R_conut)
     begin
         pluse_out1=1'b1;
         pluse_out2=1'b0;
         pluse_out3=1'b0;
         pluse_out4=1'b0;
      end
     else if ((count>R_conut)&(count<=R_conut*2))
     begin
         pluse_out1=1'b0;
         pluse_out2=1'b1;
         pluse_out3=1'b0;
         pluse_out4=1'b0;
      end
    else if ((count>R_conut*2)&(count<=R_conut*3))
     begin
         pluse_out1=1'b0;
         pluse_out2=1'b0;
         pluse_out3=1'b1;
         pluse_out4=1'b0;
      end
    else if ((count>R_conut*3)&(count<=R_conut*4))
     begin
         pluse_out1=1'b0;
         pluse_out2=1'b0;
         pluse_out3=1'b0;
         pluse_out4=1'b1;
      end
    else
     begin
        pluse_out1=1'b0;
        pluse_out2=1'b0;
        pluse_out3=1'b0;
        pluse_out4=1'b0;
     end
 end
 endtask

不定状态消失：