#FPGA学习笔记# 计数器的实现

一、项目原理

500ms，led翻转一次，系统时钟为50M~20ns;

计数25_000_000次

二、实验代码

//项目文件
module Count(clk,rst,led);
input clk;
input rst;
output reg led;

reg [24:0]count_i;
//产生一个每10ns翻转的时钟
always @(posedge clk or negedge rst)
	if(!rst)//低电平
		count_i <= 25'd0;
	else if(count_i == 25'd24_999_999)
		count_i <= 25'd0;
	else
		count_i <= count_i + 1'b1;
//灯翻转
always @(posedge clk or negedge rst)
	if(!rst)
		led <= 1'b1;
	else if(count_i == 25'd24_999_999)
		led <= ~led;
	else 
		led <= led;
endmodule

//测试文件
`timescale 1ns/1ns
`define clock_period 20
module TestCount;
reg i_clk;
reg i_rst;
wire o_led;
Count count0(
	.clk(i_clk),
	.rst(i_rst),
	.led(o_led)
	);
	initial
		i_clk = 1;
	always #(`clock_period/2)
		i_clk = ~i_clk;
	initial begin
		i_rst = 1'b0;
		#(`clock_period * 200)
		i_rst = 1'b1;
		#2000000000;
		$stop;
	end
	
endmodule	

三、电路截图