基本时钟50m晶振
module Clk_1(clk_50m,clk_1);
input clk_50m;
output reg clk_1;
integer cnt;//定义计数器寄存器
//计数器计数进程
always@(posedge clk_50m)
if(cnt == 24_999_999)begin //50m的一半
cnt<=0;clk_1=~clk_1;
end
else
cnt<=cnt+1;
endmodule
输出clk_1即为1Hz时钟
频率计数器项目地址:https://github.com/XinluHuang/Digital-frequency-meter