【牛客网刷题系列 之 Verilog快速入门】~ 四选一多路器

0. 前言

从今天开始，决定开始新的一个板块，那就是针对牛客网上边的Verilog题目做一个完整的学习，这里有两个目的，其一是记录一下自己的学习过程；其二是为后边学习这方面的同学提供一个参考，争取做到平均每日更新一篇的准备，哈哈哈！希望可以坚持下去，欢迎大家批评指正（点赞收藏关注走一波）！！！

1. 四选一多路器

仙人指路，刷题源地址点击就送

1.1 题目描述

制作一个四选一的多路选择器，要求输出定义上为线网类型.

1.1.1 状态转换

d0 11
d1 10
d2 01
d3 00

1.1.2 信号示意图

1.1.3 输入描述

输入信号 d1,d2,d3,d4 sel
类型 wire

1.1.4 输出描述

输出信号 mux_out
类型 wire

1.2 解题思路

首先，有5个输入信号，其中sel控制是哪一个数据输出，道理很简单，通过看波形就可以明白，话不多说，直接上代码！！！

1.3 代码实现

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
    reg [1:0] mux_out_temp;
    always @ (*) begin
        case (sel)
            2'b00 : mux_out_temp = d3;
            2'b01 : mux_out_temp = d2;
            2'b10 : mux_out_temp = d1;
            2'b11 : mux_out_temp = d0;
            default : mux_out_temp = d3;
        endcase
    end

    assign mux_out = mux_out_temp;
//*************code***********//
endmodule

1.3.1 代码说明

Q1：为什么要定义一个reg类型的2位变量呢？
A：因为always块中赋值语句必须是reg型的，wire类型是不可以的，wire相当于是一根线，而reg相当于是一个寄存器。

1.4 测试文件

`timescale 1ns / 100ps
module mux4_1_tb;
	reg[3:0]d0;
	reg[3:0]d1;
	reg[3:0]d2;
	reg[3:0]d3;
	reg[1:0]select;
	wire[3:0]out;
	mux4_1 u1(.d0(d0),.d1(d1),.d2(d2),.d3(d3),.out(out),.select(select));
initial begin
		
d0 = 0;d1=0;d2=0;d3=0;

d0=0;		
		
select = 0;
		
#100;
  

d0=1;		
		
select = 0;
		
#100;
 


d0=2;		
		
select = 0;
		
#100;
 


d0=3;		
		
select = 0;
		
#100;
 


d0=4;		
		
select = 0;
		
#100;
 
    

d0=5;		
		
select = 0;
		
#100;
 


d0=6;		
		
select = 0;
		
#100;
 


d0=7;		
		
select = 0;
		
#100;
 


d0=8;		
		
select = 0;
		
#100;
 

d0=9;		
		
select = 0;
		
#100;
 	

d0=10;		
		
select = 0;
		
#100;
 	
d0=11;		
		
select = 0;
		
#100;
 
	
d0=12;		
		
select = 0;
		
#100;
 
select = 0;
d0=13;		
		
select = 0;
		
#100;
 

d0=14;		
		
select = 0;
		
#100;
 

d0=15;		
		
select = 0;
		
#100;
 

d1=0;
d0=0;	
select = 1;

#100

d1=1;	
select = 1;

#100

d1=2;	
select = 1;

#100

d1=3;	
select = 1;

#100

d1=4;	
select = 1;

#100

d1=5;	
select = 1;

#100

d1=6;	
select = 1;

#100

d1=7;	
select = 1;

#100

d1=8;	
select = 1;

#100

d1=9;	
select = 1;

#100

d1=10;	
select = 1;

#100

d1=11;	
select = 1;

#100

d1=12;	
select = 1;

#100

d1=13;	
select = 1;

#100

d1=14;	
select = 1;

#100

d1=15;	
select = 1;

#100

d2=0;
d1=0;	
select = 2;

#100

d2=1;	
select = 2;

#100

d2=2;	
select = 2;

#100

d2=3;	
select = 2;

#100

d2=4;	
select = 2;

#100

d2=5;	
select = 2;

#100

d2=6;	
select = 2;

#100

d2=7;	
select = 2;

#100

d2=8;	
select = 2;

#100

d2=9;	
select = 2;

#100

d2=10;	
select = 2;

#100

d2=11;	
select = 2;

#100
d2=12;	
select = 2;

#100
d2=13;	
select = 2;

#100
d2=14;	
select = 2;

#100
d2=15;	
select = 2;

#100


d3=0;	
d2=0;
select = 3;

#100

d3=1;	
select = 3;

#100

d3=2;	
select = 3;

#100

d3=3;	
select = 3;

#100

d3=4;	
select = 3;

#100

d3=5;	
select = 3;

#100

d3=6;	
select = 3;

#100

d3=7;	
select = 3;

#100

d3=8;	
select = 3;

#100

d3=9;	
select = 3;

#100

d3=10;	
select = 3;

#100

d3=11;	
select = 3;

#100

d3=12;	
select = 3;

#100

d3=13;	
select = 3;

#100

d3=14;	
select = 3;

#100

d3=15;	
select = 3;

#100
	
#100;

$stop;
$finish;		
end
endmodule

1.5 仿真波形

根据上述观察后即可发现功能实现。

参考文献

测试用例参考

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