调用FPGA内部乘法器

1.当两个变量相乘

2.变量与常数相乘

3.要求乘法器/加法器不使用DSP block实现
在synplify pro中有一个编译指令syn_multstyle，可以实现这个功能，参见synplify pro帮助文件中的说明：

syn_multstyle Attribute 
Attribute; Lattice (LatticeECP2S/ECP2M/ECP2, LatticeECP/EC, LatticeXP2/XP, Lattice SC/SCM, MachXO, and ORCA). This attribute determines how multipliers are implemented: as dedicated hardware multiplier blocks or as logic. 
This attribute only applies to families that use DSP blocks on the device. You can use the block_mult value to implement dedicated hardware DSP blocks. To override this behavior, specify a value of logic.  
Verilog Syntax and Example 
object /* synthesis syn_multstyle = "block_mult | logic" */ ; 
module mult(a,b,c,r,en);
input [7:0] a,b;
output [15:0] r;
input [15:0] c;
input en;
wire [15:0] temp /* synthesis syn_multstyle="logic" */;
assign temp = a*b;
assign r = en ? temp : c;
endmodule

使用方法：先给 ab 赋值给一个wire型变量，然后给这个变量施加/ synthesis syn_multstyle = “logic” /的编译指令，然后再用寄存器锁存该变量。
虽然逻辑功能一样，但是为了使用/ synthesis syn_multstyle = “logic” */只能如此操作。

parameter WIDTH = 16;
wire [WIDTH*2-1:0] mult_keep /* synthesis  syn_multstyle = "logic" */ ; 
assign mult_keep = a*b;
reg [WIDTH*2-1:0] mult /* synthesis  syn_multstyle = "logic" */ ;

always @(posedge clk or posedge rst) 
     begin
        if (rst)
           mult = 32'd0;
          else
           mult = mult_keep;
      end