ERROR:Pack:2780/Place:1239

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最新推荐文章于 2023-01-17 15:24:32 发布

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分类专栏： FPGA-debug篇文章标签： fpga

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MAP报错
ERROR:Pack:2780 - The register
“U0_ddr_dut/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_ctl_io/gen_cs_n[3]…u_ff_cs_n” has the property IOB=FORCE, but it did not join an IO component
because it is not connected to any IO element.
好像是因为CS的位宽不匹配（ip核与设计顶层代码）
修改方法：
cs_n以及odt是由你选择的数据位宽决定的，我的设计本来是32位数据，我ip核生成的时候选成了64（4嘛4）位，导致我只能进去改ip核顶层的位宽（手动2嘛2）
改完了，这个错解决了，马上报下面这个

xilinx社区回答

ERROR:Place:1239 - A core generated by the Memory Interface Generator (MIG) has
been detected in your design but not all of the corresponding IO are locked.
All IO are required to be locked according to the MiG guidelines to ensure
that proper timing can be met. Please review your user constraints file
(*ucf) to ensure that all of these IO are locked. For more information on
MIG IO placement rules, please see the Xilinx Memory Interface Generator
(MIG) User Guide. The following IO are not locked:
ddr2_dq<32>
DQ的位宽与实际约束不符，我ucf里面只约束了32位数据惊不惊喜意不意外

xilinx社区中文显示太ex了,一会就英文一会就英文，注册，改密码，反应迟钝，烦死崽了，看到满篇的英文我还是劝退，六级没有什么用，渣还是渣，今日份2小时暴走