VHDL 赋值语句、顺序语句与结构描述方式

 

更正：把上面那句话改成“不在意”。

有限状态机：

library ieee;
use ieee.std_logic_1164.all;
entity status is
  port(clk,k:in std_logic;
			situation:out std_logic_vector(1 downto 0));
end status;
architecture rtl of status is
 type state_type is(s0,s1,s2,s3);
 signal state:state_type;
begin 
  one_process:process(k,clk)
begin 
  if(clk'event and clk='1')  then
    case state is
       when s0 => if(k='1') then
                state<=s0;
               else 
                state<=s1;
               end if;
       when s1 => if(k='1') then
                state<=s2;
               else 
                state<=s1;
               end if;
       when s2 => if(k='1') then
                state<=s2;
               else 
                state<=s3;
               end if;
       when s3 => if(k='1') then
                state<=s0;
               else 
                state<=s3;
               end if;
    end case;
  end if;
 end process;
with state SELECT
situation<="00" when s0,
				"01" when s1,
				"10"when s2,
				"11"when s3;
end rtl;