【FPGA学习笔记】VHDL学习笔记（三）顺序语句

一、 赋值语句

1、变量赋值：用“ ：= ”

a := 2;
b := 3.0;

2、信号赋值用“<=”,信号赋值和信号值的更新之间有一定的延时

a<=b;

二、IF 语句

IF语句简单例子：四选一数据选择器。

--if 语句
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux41 IS
	PORT (d0 : IN STD_LOGIC;
		  d1 : IN STD_LOGIC;
		  d2 : IN STD_LOGIC;
		  d3 : IN STD_LOGIC;
		  sel :IN STD_LOGIC_VECTORa(1 DOWNTO 0);
		  q   :out STD_LOGIC);
END mux41;
ARCHITECTURE rtl OF mux41 IS
BEGIN
	PROCESS (d0,d1,d2,d3,sel)
	BEGIN
		IF(sel == "00")THEN
		q <= d0;
		ELSIF(sel == "01")THEN
		q <= d1;
		ELSIF(sel == "10")THEN
		q <= d2;
		ELSE 
		q <= d3;
		END IF;
	END PROCESS;
end rtl;

三、CASE语句

case例子：仍然是四选一数据选择器（只写了结构体部分，实体同上）

--case 语句
ARCHITECTURE rtl OF mux41 IS
BEGIN
	PROCESS (d0,d1,d2,d3,sel)
	BEGIN
		CASE SEL IS
			WHEN "00" => q <= d0;
			WHEN "01" => q <= d1;
			WHEN "10" => q <= d2;
			WHEN "11" => q <= d3;
			WHEN OTHERS => q <= 'Z';
		END CASE;
	END PROCESS;
END rtl;

四、LOOP语句

1、FOR LOOP

--FOR LOOP
FOR 循环变量 IN 范围 LOOP
	顺序处理语句;
END LOOP;

例子：奇偶校验电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL 
ENTITY check IS
	PORT(
		a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		y : OUT STD_LOGIC);
END check; 
ARCHITECTURE rtl OF check IS
	BEGIN
	PROCESS(a)
		VARIABLE tmp :STD_LOGIC;
		VARIABLE i :INTEGER;
	BEGIN	
		tmp := '0';
		FOR i IN  0 TO 7 LOOP
			tmp := tmp XOR a(i);
		END LOOP;
		y <= tmp;
	END PROCESS;
END rtl;

2、WHILE LOOP

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL 
ENTITY check IS
	PORT(
		a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		q : OUT STD_LOGIC);
END check;

ARCHITECTURE behave OF check IS
VARIABLE tmp :STD_LOGIC;
VARIABLE i :INTEGER;
BEGIN
	PROCESS
	tmp := '1';
	i := 0;
	WHILE (i < 8) LOOP
		BEGIN
			tmp :=tmp AND a(i);
			i :i=1;
		END LOOP;
	END PROCESS;
END behave;

五、跳出循环：NEXT,EXIT

NEXT:用在LOOP循环内部，用于跳出本次循环。

--当i=j的时候，跳出L2循环，来到L1标号处
L1:WHILE i<10 LOOP
	L2:WHILE j<10 LOOP
		NEXT L1 WHEN i = j;
	END LOOP L2;
END LOOP L1;

EXIT:跳出并结束整个循环状态

EXIT [标号] [WHEN 条件]；

六、RETURN语句

return语句可用于函数或者过程体中。
1、用于函数中： return语句必须含有表达式，而且它是结束函数的唯一条件。

2、用于过程体中 ：return语句不能含有表达式，可以中断执行，跳出过程。

--求最大值的函数（函数）
FUNCTION maximun(a,b :INTEGER) RETURN INTEGER IS
VARIABLE tmp :INTEGER
BEGIN
	IF (a > b) THEN 
	tmp := a;
	ELSE 
	tmp := B;
	END IF;
	RETURN tmp;
END maximun;

--描述RS触发器(过程体)
PROCEDURE rs (SIGNAL s,r : IN STD_LOGIC;
			  SIGNAL q,nq : OUT STD_LOGIC) IS
BEGIN
	IF (s = '1' AND r = '1') THEN 
		REPORT "Foribidden state :s and r are equal to '1'  " 
		RETURN;
	ELSE	q <= s AND nq AFTER 5ns;
			nq <= r AND q AFTER 5ns;
	END IF;
END PROCEDURE rs;

七、NULL语句

占位空操作，不执行任何操作