Implement the following circuit:
实现以下电路:
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
运行结果:
分析:
或非门,先或后非
Implement the following circuit:
实现以下电路:
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
运行结果:
分析:
或非门,先或后非