【Verilog_16】: 序列发生器、序列校验器、序列检测器一条龙服务

序列发生器、序列校验器、序列检测器一条龙服务

序列发生器：产生指定序列

author : Mr.Mao
e-mail : 2458682080@qq.com


module seq_generator(
    input            clk ,
	 input            rst_n ,
	 output    reg    data 
);

//规定输出数据
    parameter HEAD  = 8'b1110_1000 ;
	 parameter DATA0 = 8'b1111_0000 ;
	 parameter DATA1 = 8'b0000_1111 ;
	 parameter DATA2 = 8'b1111_1111 ;
	 parameter DATA3 = 8'b1010_1010 ;
	 parameter SUM   = 8'b1010_1000 ;
	 
	 reg [5:0] bit_cnt ;

//模为48的计数器
always @ (posedge clk or negedge rst_n)
begin 
     if(!rst_n)
	      bit_cnt <= 1'b0 ;
	
     else if(bit_cnt < 6'd47)
	      bit_cnt <= bit_cnt + 1'b1 ;
	
     else
	      bit_cnt <= 1'b0 ;
end


//输出赋值
always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
	     data <= 1'b0 ;
		 
	 else
	     case(bit_cnt[5:3])
		        3'b000 : data <= HEAD[3'd7-bit_cnt[2:0]]    ;
			    3'b001 : data <= DATA0[3'd7-bit_cnt[2:0]]	;
				3'b010 : data <= DATA1[3'd7-bit_cnt[2:0]]	;
				3'b011 : data <= DATA2[3'd7-bit_cnt[2:0]]	;
				3'b100 : data <= DATA3[3'd7-bit_cnt[2:0]]	;
				3'b101 : data <= SUM[3'd7-bit_cnt[2:0]]     ;
			endcase
end

endmodule

序列校验器：检验序列器产生的序列是否和我们要求的一样

author : Mr.Mao
e-mail : 2458682080@qq.com


module seq_rd(
     input           clk ,
	  input           rst_n ,
	  input           data_in ,
	  
	  output   [7:0]  out_data0 ,
	  output   [7:0]  out_data1 ,
	  output   [7:0]  out_data2 ,
	  output   [7:0]  out_data3 ,
	  output          out_check_flag 
);


     reg      [5:0]   bit_cnt ;
	  reg      [40:0]  data ;
	  reg      [7:0]   sum ;
	  wire     [7:0]   sum_check ;
	  wire             head_check ;
	  
assign  {out_data0, out_data1, out_data2, out_data3, sum_check} = data[39:0] ;
assign  out_check_flag = ((bit_cnt == 6'd40) && (sum_check == sum)) ;


seq_detect u_seq_detect(
     .clk              (clk) ,
	  .rst_n            (rst_n) ,
	  .data_in          (data_in) ,
	  .sout             (sout)
);


always @ (posedge clk or negedge rst_n)
begin 
      if(!rst_n)
		     begin 
			      bit_cnt <= 6'b0 ;
					data <= 40'b0 ;
			  end
			  
		else if(head_check) 
		     begin
			      bit_cnt <= 6'd1 ;
					data[0] <= data_in ;
			  end
			  
		else if(bit_cnt < 6'd40)
		     begin
			      bit_cnt <= bit_cnt + 1'b1 ;
					data[0] <= data_in ;
					data[40:1] <= data[39:0] ;
				end
		
		else  
		     begin
			      bit_cnt <= 6'b0 ;
			  end
end


always @ (posedge clk or negedge rst_n)
begin 
      if(!rst_n)
		    sum <= 8'b0 ;
			
		else if(head_check)
		    sum <= 8'b0 ;
			 
		else if(bit_cnt[2:0] == 3'b111 && bit_cnt[5] != 1'b1)
		    sum <= sum + {data[6:0], data_in} ;
end

endmodule

序列检测器：检测要求序列

author : Mr.Mao
e-mail : 2458682080@qq.com

module seq_detect(      //时序检测
      input        clk ,  //时钟输入
		input        rst_n ,  //复位信号
		input        data_in ,  //串行数据输入
		output wire  sout   //序列检测输出
);


parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8 ;

reg  [3:0]          current_state ;
reg  [3:0]          next_state ;


/*现状态的跳转*/
always @(posedge clk or negedge rst_n)
begin
     if(!rst_n)
	      current_state <= s0 ;
		else 
		   current_state <= next_state ;
end

always @(*)
begin 
     case(current_state)   /*现状态的跳转触发次状态的判断*/
	      s0 : if(data_in == 1'b1)  next_state <= s1 ; else next_state <= s0 ;
			s1 : if(data_in == 1'b1)  next_state <= s2 ; else next_state <= s0 ;
			s2 : if(data_in == 1'b1)  next_state <= s3 ; else next_state <= s0 ;
			s3 : if(data_in == 1'b0)  next_state <= s4 ; else next_state <= s3 ;
			s4 : if(data_in == 1'b1)  next_state <= s5 ; else next_state <= s0 ;
			s5 : if(data_in == 1'b0)  next_state <= s6 ; else next_state <= s2 ;
			s6 : if(data_in == 1'b0)  next_state <= s7 ; else next_state <= s1 ;
			s7 : if(data_in == 1'b0)  next_state <= s8 ; else next_state <= s1 ;
			s8 : if(data_in == 1'b0)  next_state <= s0 ; else next_state <= s1 ;
			default : next_state <= s0 ;
		endcase
end

assign sout = (current_state ==s8) ; /*检测结果输出*/

endmodule

//force data_in 1 0,0 300ns,1 400ns,0 500ns -repeat 800ns	
//这段命令在Moedelsim命令窗口执行，模拟‘11101000’	输入激励

序列检测器的testbench代码

`timescale 10 ns/ 100 ps
module seq_detect_tb();

reg clk ;
reg data_in ;
reg rst_n ;
wire sout ;


seq_detect i_seq_detect(
      .sout         (sout),
		.clk          (clk),
		.data_in      (data_in),
		.rst_n        (rst_n)
);
   
	  initial
	      begin
			clk <= 0 ;
			rst_n <= 0 ;
			#10 rst_n <= 1'b1 ;
			@(negedge clk)
			repeat(10)
			   begin
				   data_in <= $random ;
					#10 ;
				end
				data_in <= 1 ;
				#10     data_in <= 1 ;
				#10     data_in <= 1 ;
				#10     data_in <= 1 ;
				#10     data_in <= 0 ;
				#10     data_in <= 1 ;
				#10     data_in <= 0 ;
				#10     data_in <= 0 ;
				#10     data_in <= 0 ;
			repeat(10)
			    begin
				    data_in <= $random ;
					 #10 ;
				 end
			#100   $stop ;
			end
			
			
		always     #5
		    begin
			    clk <= ~clk ;
			 end
endmodule